Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
1999-04-06
2001-10-02
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S099000
Reexamination Certificate
active
06297684
ABSTRACT:
TECHNICAL FIELD
The present invention is related to a circuit and a method for generating and switching between digital signals having different signal rates. More particularly, the present invention is related to encoding digital signals that have high signal rates to generate encoded signals, and further to switching such signals onto the same signal line with an arbitration signal having a low signal rate.
BACKGROUND ART
In modern electronics, it is common for an integrated circuit to generate a variety of signal types. An integrated circuit may, for example, generate data signals that convey information at a high signal rate, and may also generate arbitration signals that have a substantially lower signal rate and are useful for controlling other devices. Where signals having substantially different signal rates utilize the same signal path, various problems may arise due to the difference in signal rates. For example, a false or spurious signal commonly known as a glitch may occur in an output signal on the signal path due to the difference in signal rates.
One particularly important example occurs in computer systems having a bus that interconnects various components in accordance with IEEE Standard 1394 of the
Institute of Electrical and Electronics Engineers
. In this context, signals that have a high signal rate may include a data signal that conveys data in a signal rate range between about 100 MHz to 300 MHz, and may also include a strobe signal at substantially the same signal rate as the data signal that a receiving device may use to maintain synchronization with the data signal. The signals that have a low signal rate may include an arbitration signal having a signal rate of about 50 MHz. Such arbitration signals are specified in IEEE Standard 1394 for controlling operation of the bus and various devices connected to the bus.
One conventional approach for switching signals that have different signal rates onto the same signal path is to connect the signal sources of the signals to the signal path by means of a conventional multiplexor. If the maximum difference in signal rates between the signal sources exceeds about 100 MHz, this conventional approach does not operate properly. The difference in signal rates typically causes the multiplexor to generate a glitch at output. The glitch may be interpreted as being part of a data signal, and consequently may generate data errors. A glitch occurring when the multiplexor switches an arbitration signal onto the bus may be interpreted as being part of the arbitration signal, and could cause a receiving device to malfunction. Glitches occur at or near the beginning of a switched signal, and thus may interfere with signal prefixes, such as various signal prefixes required by IEEE Standard 1394 to indicate transition between signal types.
A further problem in this field is a one-cycle delay introduced to data and strobe signals by a conventional non-memoryless encoding circuit and method described in IEEE Standard 1394 for generating strobe signals. More particularly, IEEE Standard 1394 describes a conventional encoder for encoding data signals by means of recursion to generate strobe signals. This conventional encoder supplies the data signal to one input of a first XOR gate, and to the D input of a first D flip-flop. A delayed data signal supplied by the Q output of the first D flip-flop is fed back to the other input of the first XOR gate, and the output of the first XOR gate drives the first input of a second XOR gate. The output of the second XOR gate drives the D input of a second D flip-flop. The Q output of the second D flip-flop supplies the strobe signal. The /Q output supplies an inverted strobe signal that is fed back to the second input of the second XOR gate. Both D flip-flops are clocked by the same clock signal.
Clearly, this encoding is recursive due to operation of the D flip-flops. The encoding requires feedback from two sources. Moreover, the data signal must be delayed by at least one clock cycle to generate the strobe signal, and the data signal supplied to the bus will actually be a delayed data signal that is essentially a copy of the original data signal delayed by at least one full clock cycle. This added latency slows down the transmission of data to other devices that are connected to the bus, and thus is highly undesirable.
There is thus a continuing need in the electronics arts for an improved circuit and an improved method for connecting a signal path to signal sources that supply signals at substantially different signal rates. Such a circuit and method preferably prevents output glitches from arising during switching operations. It is highly desirable for such circuit and method to be implemented in conformance with IEEE Standard 1394, and to support data and strobe signal rates that may exceed 200 MHz. An improved switching circuit is needed to drive the output buffers on an integrated circuit (IC) chip. Such an improved circuit preferably requires minimal space on the IC chip to implement.
There is also a need for an improved encoder and encoding method for encoding digital signals in parallel. Preferably such encoder and encoding method can be implemented to generate strobe signals in accordance with IEEE Standard 1394. To minimize latency of data and strobe signals, it is highly desirably to generate such strobe signals without use of recursion. Further it is highly desirable for at least one embodiment of the encoder to supply strobe signals according to IEEE Standard 1394 without introducing latency penalties.
DISCLOSURE OF INVENTION
An improved circuit and an improved method are disclosed that support switching operations between digital signals that may have substantially different signal rates. The improved circuit and method are particularly well suited for switching a bus between sources of data or strobe signals and sources of arbitration signals in conformance with IEEE Standard 1394. The improved circuit can be implemented using a minimal amount of space on an integrated circuit (IC) chip, and beneficially prevents glitches during switching operations even where the signal rate difference between switched signals may exceed 50 MHz. The improved circuit does not require a large number of transistors or other component elements to fabricate, and conveniently can be implemented with standard logic gates and shift registers.
In accordance with one aspect of the invention, a multiplexor for switching between a first digital signal, such as a data or strobe signal conforming to IEEE Standard 1394, and a second digital signal, such as an arbitration signal conforming to IEEE Standard 1394, is responsive to a control signal having a first state that designates a first digital signal and a second state that designates a second digital signal. The multiplexor includes a controller having an input for receiving the control signal, a first output that asserts a third state during a first interval of time that begins substantially when the control signal attains the first state and ends after the control signal remains in the second state for a second interval of time, and a second output that asserts a fourth state during a third interval of time that begins substantially when the control signal attains the second state and ends after the control signal remains in the first state for a fourth interval of time. The multiplexor also includes a first switch having an input for receiving the first digital signal, a control terminal coupled to the first output of the controller, and an output for supplying a first intermediate signal representing the first digital signal while the third state is asserted; a second switch having an input for receiving a second digital signal, a control terminal coupled to the second output of the controller, and an output for supplying a second intermediate signal representing the second digital signal while the fourth state is asserted; and an output coupled to the outputs of the first and second switches for supplying an output signal.
In accordance with ano
Chiang Kuang-Yu
Uyehara Clinton
Seiko Epson Corporation
Wells Kenneth B.
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