Circuit and method for suppressing gate induced drain leakage

Details Circuit and method for suppressing gate induced drain leakage Circuit and method for suppressing gate induced drain leakage

2006-12-15

2009-12-29

Zweizig, Jeffrey S (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S112000

Reexamination Certificate

active

07639066

ABSTRACT:
An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

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patent: 7205807 (2007-04-01), Svensson et al.
patent: 7224195 (2007-05-01), Pilling et al.

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