Circuit and method for split bias enable/inhibit memory operatio

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307494, H03K 1756, H03K 522

Patent

active

045785945

ABSTRACT:
A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I.sub.D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I.sub.D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I.sub.D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers. Circuit operation is inhibited by splitting a bias signal supplied to the differential amplifiers. When inhibited, the circuit steers current I.sub.D along a predetermined one of said first and second current paths. This produces a corresponding continual predetermined logic output signal without regard to the differential input signal present at the first and second input terminals. Circuit operation is enabled by balancing the bias signal supplied to the differential amplifiers. When enabled, both differential amplifiers connected to the output stage are operative.

REFERENCES:
patent: 3838296 (1974-09-01), Mcleod
patent: 4037118 (1977-07-01), Sieborger et al.
patent: 4349750 (1982-09-01), Geurts
patent: 4382197 (1983-05-01), Kiyozuka

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