Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-21
2003-01-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185250, C365S205000, C365S207000
Reexamination Certificate
active
06512697
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a sense amplifier for a semiconductor memory, and more particularly, to a circuit and method for speed and stability enhancement for a sense amplifier.
BACKGROUND OF THE INVENTION
A sense amplifier is included in a semiconductor memory for read-out of data from memory cells, the speed and the stability of the sense amplifier thus dominate the performance of the memory.
FIG. 1
is the architecture of a typical semiconductor memory circuit, which includes a cell array
12
consisting of a plurality of storage transistors that are illustratively shown only part of them for simplification. An X decoder
14
and a Y decoder
16
are employed for selection of a specific memory cell from the cell array
12
by word lines WL
1
, WL
2
. . . , WLM from the X decoder
14
and bit lines YS
1
, YS
2
, . . . , YSN from the Y decoder
16
respectively in the column and row directions. The selected memory cell will be connected to a data line DL through a bit line select transistors
18
and then read out from the data line DL by a sense amplifier
20
to transmit a data signal OUT from the output of the sense amplifier
20
. The basic operation of a sense amplifier is shown in
FIG. 2
, and the timing diagram is provided in
FIG. 3. A
sense amplifier
22
includes a transmission transistor MN
1
separating a data node VD and a sense node VZ on two sides of the transistor MN
1
with the data node VD connected to the data line DL to provide a path for read-out of data and the sense node VZ to transmit the data signal OUT through an output stage, for instance an inverter X
2
herewith. The total capacitance seen from the data node VD and the sense node VZ are C
1
and C
2
respectively. When the selected memory cell is a conductive transistor, i.e., in a low state, there will be a cell current Icell appeared on the data line DL; contrarily, when the selected cell is a non-conductive transistor, i.e., in a high state, the cell current Icell on the data line DL is zero. During the sense amplifier
22
reading a low state, the data node VD is discharged by the cell current Icell and results in a sense current Isense conducted by the transmission transistor MN
1
, thus the voltage on the sense node VZ drops to a relative low level. During the sense amplifier
22
reading a high state, the cell current Icell is zero and the sense current Isense is zero or extremely small, such that the voltage on the sense node VZ is maintained a relative high level. When reading a low state, a time delay is present due to the transition of the transmission transistor MN
1
from shut-down to turned-on, which induces a low sense speed. Furthermore, the speed to turn on the transmission transistor MN
1
is even reduced for the voltage feedback from the data node VD to the transmission transistor MN
1
through the NOR gate X
1
. On the other hand, when reading a high state, the transmission transistor MN
1
could be undesired turned on by noise, thereby resulting in an unstable operation. Moreover, the data node VD could be overcharged to a very high level after several reading cycles, that will further reduces the turn-on speed of the transmission transistor MN
1
and so the sense speed.
To enhance the stability of a sense amplifier, as shown in
FIG. 4
, a prior art applies an additional charging to the sense node VZ of the sense amplifier
24
by introduction of a current apparatus, and the timing diagram is shown in
FIG. 5. A
transistor MP
2
is biased by a voltage BIAS to generate a leakage current for the sense node VZ to obtain a better stability.
Another proposed arrangement is shown in
FIG. 6
, in which a discharge current apparatus MN
3
is introduced into a sense amplifier
26
and connected to the data node VD under the control of a switch transistor MN
2
, and the timing diagram is shown in FIG.
7
. The data node VD is discharged by the sense amplifier
26
during the precharge period to enhance the speed to turn on the transmission transistor MN
1
.
Smarandoiu et al. in U.S. Pat. No. 5,390,147 improve a sense amplifier with a lubrication current mirror connected to a data node and a reference node in combination with a feedback by a reference current mirror to enhance the speed of the sense amplifier. However, this manner the sense current is affected by the lubrication current and the reference current through the feedback in this arrangement. As a result, when not in an ideal situation, for example, the reference current variation due to the process drifting, a variation of the sense current will be induced, thereby reducing the sense speed and even a wrong sense result.
Therefore, it is desired a further improvement on a sense amplifier.
SUMMARY OF THE INVENTION
One object of the present invention is the sense speed and stability improvement of a sense amplifier by a connection of an offset current apparatus to the data node on one side of a transmission transistor to ensure that the transmission transistor does not shut down in the absence of current resulted from a memory cell and the data node will not be overcharged to a very high voltage so as to enhance the sense speed of the sense amplifier. A leakage current apparatus is further connected to the sense node on another side of the transmission transistor to improve the stability of the sense amplifier. The leakage current is derived from the offset current by a current mirror to obtain a good control of the operation and performance of the sense amplifier. There is also a discharge current apparatus connected to the data node to, compensate the leakage current from the transmission transistor.
REFERENCES:
patent: 5390147 (1995-02-01), Smarandoiu et al.
patent: 6055187 (2000-04-01), Dallabora et al.
Li Hsiang-Pang
Shih Yi-Te
Macronix International Co. Ltd.
Pham Ly Duy
Rabin & Berdo P.C.
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