Circuit and method for self trimming frequency acquisition

Details Circuit and method for self trimming frequency acquisition Circuit and method for self trimming frequency acquisition

2000-05-31

2004-10-19

Chin, Stephen (Department: 2734)

Pulse or digital communications

Transceivers

C375S375000, C327S048000

Reexamination Certificate

active

06807225

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, generally, to an improved circuit and method for frequency acquisition and, more particularly, to a self trimming circuit and method for frequency acquisition and clock recovery.
BACKGROUND OF THE INVENTION
Generally, all communication systems include a transmitter, a receiver and a communication channel. A fiber optic communication system is a lightwave system employing optical fibers as the communication medium. Optical fibers transport the optical signal (lightwave) with relatively little power loss. Power or fiber loss is largely due in part to noise or jitter in the signal. Signal noise can be caused by many different sources, such as, for example, thermal noise, shot noise and imperfect fiber.
Power loss consideration is an important design parameter. In particular, the power loss determines the repeater spacing of a long-haul lightwave system. During normal signal transmission it is necessary to periodically regenerate the optical signal with a repeater. Repeater stations include an optical receiver-transmitter pair that detects the incoming optical signal, recovers the electrical bit stream, and converts it back to an optical bit stream by modulating the transmission. The optical receiver portion typically consists of a digital optical receiver. The digital optical receiver includes a clock and data recovery (CDR) component comprising a decision circuit and a clock recovery circuit.
In a typical repeater, the decision circuit first compares the output from the channel to a threshold level at a sampling time determined by the clock-recovery circuit. Next, the decision circuit decides whether the signal corresponds to bit “1” or bit “0.”
The purpose of the clock-recovery circuit is to isolate a spectral component at a frequency (f) equal to the bit rate (B) from the received signal. This component provides information about the bit slot to the decision circuit and helps to synchronize the bit sampling process. In the case of RZ (return-to-zero) format, a spectral component at f=B is present in the received signal and a narrow bandpass filter such as a surface-acoustic-wave (SAW) filter can effectively isolate this component. Clock recovery is more difficult in the case of NRZ (non-return-to-zero) format because the received signal lacks a spectral component at f=B. NRZ is the standard data format in SONET (synchronous optical network) systems and SONET is the standard for the telecommunications industry.
The CDR circuit restores and retimes the NRZ bit sequence by extracting the clock signal from the received data. Because the spectrum of a NRZ random bit sequence does not have a spectral component at the bit rate f=B, this spectral component has to be created using nonlinear signal processing. The component at f=B is generated, filtered and phase aligned to the NRZ data to yield a clock signal. In general, a phase and frequency locked loop (PFLL) is used to perform both the filtering and the phase alignment. The incoming data is resampled with a clean clock to filter, for example, jitter present on the data.
The clean clock is provided by a voltage controlled oscillator (VCO). The frequency and phase of the NRZ data controls the input voltage to the VCO in a loop configuration. The VCO frequency and phase are adjusted in response to the input NRZ data frequency and phase. Ideally, the VCO free running frequency (i.e., without control from the loop) should be as close as possible to the frequency of the incoming data. However, in an integrated CDR, the VCO free running frequency can vary considerably from the data frequency (e.g., up to a ±50% difference). In fact, the data frequency may be outside the maximum frequency tuning range of the VCO or outside the maximum range of the frequency detector. In both cases, it is very difficult for the loop configuration to effectively adjust the VCO frequency to the data frequency.
The CDR generally has two loops: a phase loop to clean up and lock the phase; and a frequency loop to adjust the VCO frequency to the incoming data frequency. Referring now to
FIG. 1
, an exemplary schematic of a two loop CDR of the prior art is shown. As illustrated, CDR
100
comprises a phase loop
102
, a frequency loop
104
, a VCO
106
, and a frequency window
112
. Phase loop
102
includes a phase detector
108
. Phase detector
108
has a very narrow frequency range and, therefore, the VCO frequency must be close to the incoming data frequency for the phase loop to lock. Frequency loop
104
includes a frequency detector
110
having a wider frequency acquisition range than phase loop
102
, typically around plus or minus twenty five percent (±25%) if working with no external reference. Frequency loop
104
receives the incoming NRZ data when the CDR system is initialized.
Frequency detector
110
can be a frequency detector (FD) such as the Pottbäcker frequency detector. Referring now to
FIG. 2
, the Pottbäcker FD
200
includes a phase detector (PD)
202
, a quadrature phase detector (QPD)
204
, a frequency detector (FD)
206
, and an output
208
. It should be noted that output
208
is averaged by a low pass filter
210
. In fact, the output of frequency detector
110
and phase detector
108
of
FIG. 1
are also averaged by low pass filter (LPF
2
) and (LPF
1
) respectively. In PD
202
and QPD
204
, the VCO signal is sampled by the NRZ input signal. The two beat notes (Q
1
and Q
2
of FD
206
) are subsequently processed in FD
206
. The output
208
is the average of Q
3
. For a complete understanding of the Pottbäcker FD, refer to: A. Pottbäcker, U. Langmann, and H. -U. Schreiber, “An 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, December 1992, the disclosure of which is incorporated herein by reference.
Referring again to
FIG. 1
, frequency detector
110
changes the frequency of VCO
106
using the incoming data frequency as the reference. The incoming data frequency is compared to the VCO frequency by frequency detector
110
. If the incoming data frequency is higher than the VCO frequency, frequency detector
110
will output a positive average and the frequency of VCO
106
will be driven higher. Conversely, if the data frequency is lower than the VCO frequency, the average will be negative and the frequency of VCO
106
will be driven lower.
The change of VCO
106
frequency continues until the frequency of VCO
106
nears the incoming data frequency (e.g., typically around ±1% difference). Frequency window
112
is a counter that monitors the frequencies of loop
104
comparing the frequencies of the beat between the incoming data and the VCO, namely, the output of PD
202
or QPD
204
of FIG.
2
. Once the frequencies approach an acceptably low difference, frequency window
112
sends a signal to shut off loop
104
causing a switch coupled to the input of VCO
106
to engage phase loop
102
.
The frequency acquisition range of frequency detector
110
is wider than the range of phase detector
108
, however the range is nonetheless limited. The VCO free running frequency must lie within approximately ±25% of the output of frequency detector
110
for loop
104
to effectively change the VCO frequency. However, in operation the difference between the VCO frequency and the bit rate (B) can be as high as ±50%.
Referring now to
FIG. 3
, an exemplary averaged output (e.g., output
208
after low pass filter
210
) of a conventional.(e.g., Pottbäcker) frequency detector is shown. For exemplary purposes only, the frequency is illustrated as varying from zero to twice the incoming data frequency. As we know, NRZ format lacks a spectral component at f=B. As shown in,
FIG. 3
, a change of sign in average occurs at 2500 (2.5 GHz) representing the spectral component at f=B. Thus,
2500
is the center frequency or the desired lock point in the exemplary output of FIG.
3
. Under ideal conditions, the

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