Circuit and method for selectively enabling ECL type outputs

Details Circuit and method for selectively enabling ECL type outputs Circuit and method for selectively enabling ECL type outputs

1996-06-14

1999-12-28

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327108, 326 30, H03L 500

Patent

active

060086823

ABSTRACT:
A clock circuit for selectively enabling a clock signal to be propagated, via a transmission line, to an option module when the module is coupled to the clock circuit, and for preventing propagation of the clock signal through the transmission line when the option module is decoupled from the clock circuit. The clock circuit includes a clock driving element employed within a first module and a clock receiving element employed within a second module. The clock driving element includes a clock driver, normally an amplifier connected to at least one emitter-follower transistor. A pull-up resistor is coupled to the emitter of the transistor so that, when the option module is decoupled from the transmission line, the pull-up resistor applies voltage sufficient to turn-off the transistor. Otherwise, the pull-up resistor has no effect on the clock circuit.

REFERENCES:
patent: 4888501 (1989-12-01), Sanwo et al.
patent: 4912341 (1990-03-01), Naghshineh
patent: 5132561 (1992-07-01), Coffey et al.
patent: 5508665 (1996-04-01), Chan et al.
patent: 5515005 (1996-05-01), Yoshioka
patent: 5523722 (1996-06-01), Nakano et al.
patent: 5581201 (1996-12-01), Sonner et al.

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