Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Utility Patent
1999-09-20
2001-01-02
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S277000, C327S237000, C327S407000, C327S408000
Utility Patent
active
06169438
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a circuit and method for delaying signals, and in particular, to a circuit and method for selectively delaying electrical signals using a control signal.
BACKGROUND OF THE INVENTION
Electrical circuits which process logic level signals often require a variable, dynamically controllable delay for each pulse. One example where the capability to selectively delay pulses is desirable is the CD-R/RW writing process. For CD recordable (CD-R) media, the writing process includes generation of burn holes in a thin film. For CD rewritable media (CD-RW), the writing process includes generating marks and spaces by phase-changing spots in the media.
This results in better control of the physical dimensions of each mark. Due to thermal heating effects, the length of a mark on the CD is determined not only by the on-time and the optical power of the write laser but also by the characteristics of its neighboring marks and spaces. Thus, it is desirable to individually modify the output power of each laser write pulses according to the content of neighboring marks and spaces.
SUMMARY OF THE INVENTION
The invention relates to a circuit and method for selectively delaying an electrical signal. A series of delay modules are used to provide progressively finer delays. The path through the delay modules is determined by a series of selectors which select one of a plurality of delayed signals to pass on to a subsequent delay module. Each selector is controlled by a control signal. The control signals are generated according to the desired delay to be imposed on the signal and can provide real-time delay adjustments to the logic signal.
In one aspect, the circuit of the invention includes a first delay module, a second delay module, a first selector and a second selector. The first delay module has an input to receive the signal to be delayed, a clock input and a signal output. The first selector has a first and a second input in communication with the first delay module input and first delay module signal output, respectively, a control input and an output. The second delay module has an input in communication with the first selector output, a clock input and an output. The second selector has a first, second and third input in communication with the first delay module input, the first delay module signal output and the second delay module signal output, respectively. The second selector also has an output and a control input. A selected pulse delay is generated in response to a first and a second control signal received at the first and second selector control inputs, respectively.
In one embodiment, the second selector control input includes a plurality of control lines and the second control signal includes a plurality of control bits. Each of the plurality of control lines is adapted to receive a respective control bit. In a further embodiment, each control bit is prioritized relative to the other control bits.
In one embodiment, the first selector includes a first tri-state buffer and a second tri-state buffer. The first tri-state buffer is in communication with the first delay module signal input and has a buffer enable input and an output. The second tri-state buffer is in communication with the first delay module signal output and has a buffer enable input. The second tri-state buffer also has an output which is in communication with the first buffer output.
In another aspect, the method of generating a selectively delayed signal includes the steps of receiving a signal to be delayed, generating a first delayed signal in response to a first clock delay signal having a first frequency, and selecting either the signal to be delayed or the first delayed signal as a first output signal. The method also includes the steps of generating a second delayed signal in response to a second clock delay signal having a second frequency and the first output signal, and selecting one of the signal to be delayed, the first delayed signal and the second delayed signal as the selectively delayed signal.
In one embodiment, the method includes the additional step of generating a third delayed signal in response to a third clock delay signal having a third frequency and the selected one of the signal to be delayed, the first delayed signal and the second delayed signal. In this embodiment, the step of selecting the signal to be the selectively delayed signal includes selecting one of the signals to be delayed, the first delayed signal, the second delayed signal and the third delayed signal as the selectively delayed signal.
REFERENCES:
patent: 4926423 (1990-05-01), Zukowski
patent: 5670904 (1997-09-01), Moloney et al.
Grey Phares J.
Wu Shengquan
Cox Cassandra
Oak Technology, Inc.
Wells Kenneth B.
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