Circuit and method for securing write recovery operation in a sy

Details Circuit and method for securing write recovery operation in a sy Circuit and method for securing write recovery operation in a sy

1997-06-26

1998-07-14

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, 365203, G11C 800

Patent

active

057815011

ABSTRACT:
A circuit and a method for securing a write recovery operation in a semiconductor memory device. The write recovery security circuit comprises an external signal output unit for outputting an external signal in response to a pulse signal, a external enable signal and a write recovery signal, an external signal latch unit for performing a latch operation in response to the pulse signal, the external enable signal and the write recovery signal to latch an inverted one of the external signal from the external signal output unit while a write recovery operation is performed, and a pulse generator for supplying the pulse signal to the external signal output unit and the external signal latch unit in response to the write recovery signal and transferring the inverted external signal from the external signal output unit to the external signal latch unit in response to the pulse signal. According to the present invention, the external signal is delayed for a predetermined time period when it is inputted while or after a write operation is performed. Therefore, the write operation can be performed completely.

REFERENCES:
patent: 4110840 (1978-08-01), Abe et al.
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5359722 (1994-10-01), Chan et al.
patent: 5568445 (1996-10-01), Park et al.
patent: 5687134 (1997-11-01), Sugawara et al.

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