Patent
1997-10-20
1998-11-24
Donaghue, Larry D.
395392, 395393, 395394, G06F 938
Patent
active
058420363
ABSTRACT:
An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.
REFERENCES:
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5546597 (1996-08-01), Martell et al.
patent: 5553256 (1996-09-01), Fettermen et al.
patent: 5604878 (1997-02-01), Colwell et al.
Fetterman Michael A.
Hinton Glenn J.
Martell Robert W.
Papworth David B.
Schwartz James L.
Donaghue Larry D.
Intel Corporation
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