Circuit and method for reducing the crest factor

Details Circuit and method for reducing the crest factor Circuit and method for reducing the crest factor

2004-06-03

2010-11-23

Pathak, Sudhanshu C (Department: 2611)

Pulse or digital communications

Transmitters

C375S296000, C375S297000, C375S346000, C375S260000, C370S210000, C370S481000, C455S075000

Reexamination Certificate

active

07839947

ABSTRACT:
According to the invention, a circuit for reducing the crest factor is provided:(A) with a transmit path with a data symbol to be transmitted;(B) with a model path,which is arranged in parallel with a section of the transmit path,which exhibits a model filter to which the non-oversampled data symbol to be transmitted can be supplied, the non-oversampled data symbol exhibiting a non-flat PSD power spectrum,which exhibits an analysis and evaluation circuit which is arranged following the model filter and which checks whether the time domain function of the data symbol to be transmitted exhibits within a predetermined time interval at least one maximum, the amount of which exceeds a first threshold and/or determines the associated position of the maximum within the time interval, and which, by scaling and displacing a dirac-like sample function generates a correction function in dependence on the position and the amplitude of the maximum;(C) with a subtracting device which is connected to outputs of the model path and of the transmit path and which subtracts the correction function from the data symbol to be transmitted.

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Salvekar, A.A et al., Peak-to-Average Power Ratio Reduction for Block Transmission Systems in the Presence of Transmit Filtering, IEEE International Conference on Communications, 2001, pp. 175-178.

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