Circuit and method for reducing overshoots in adaptively...

Details Circuit and method for reducing overshoots in adaptively... Circuit and method for reducing overshoots in adaptively...

2011-07-19

2011-07-19

Berhane, Adolf (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S311000, C323S312000

Reexamination Certificate

active

07982448

ABSTRACT:
Disclosed are a circuit and a method for adaptively biasing a voltage regulator with minimal output overshoot. The circuit includes an adaptive bias current mirror circuit further including a first transistor and a second transistor, the first transistor and the second transistor having source nodes coupled to a drain node of the first transistor. The circuit includes a common node coupled to the source node of the first transistor and the source node of the second transistor, wherein a source degenerate resistor is coupled to the adaptive bias current mirror circuit and is coupled to the common node and wherein the source degenerate resistor is configured to limit an output peak current of the voltage regulator circuit.

REFERENCES:
patent: 6081108 (2000-06-01), Marshall
patent: 6348835 (2002-02-01), Sato et al.
patent: 6617832 (2003-09-01), Kobayashi
patent: 6847254 (2005-01-01), Pai
patent: 7332957 (2008-02-01), Hasegawa
patent: 2001/0017537 (2001-08-01), Antheunis

Affiliated with

Also associated with

Rating

Circuit and method for reducing overshoots in adaptively... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for reducing overshoots in adaptively..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for reducing overshoots in adaptively... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2679613