Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-10-21
2003-05-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230020, C365S230030, C365S189020, C365S189040, C365S189050
Reexamination Certificate
active
06570816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memory devices and, more specifically, to devices and methods for reducing idle cycles in semiconductor memory devices, such as synchronous Static Random Access Memory (SRAM) devices.
2. Description of the Related Art
Modem synchronous SRAM devices are typically burst-oriented, which means that they perform read or write operations on a sequence of internal addresses in response to receiving a single, externally supplied address. Thus, for example, in a modern 64K×32 SRAM device with a burst length of four, a single, externally-generated address supplied to the device during a read operation causes the device to sequentially output four, 32-bit wide data words. Similarly, a single, externally-generated address supplied to the device during a write operation causes the device to sequentially write in four, 32-bit wide data words. Because internal addresses can be generated within burst-oriented SRAM devices much faster than external addresses can be latched into such devices, read and write operations occur more rapidly in burst-oriented SRAM devices than in older, non-burst-oriented SRAM devices.
Despite the speed boost provided by burst operations, read operations in modern burst-oriented SRAM devices are not as fast as is desirable. For example, as shown in
FIG. 1
, sequential read operations
10
and
12
(only a portion of read operation
12
is shown in
FIG. 1
) in a conventional burst-oriented SRAM (not shown) are separated by an idle cycle
14
, which adds to the total time it takes to perform the read operations
10
and
12
.
More specifically, the first read operation
10
is initiated at time t
0
when the address register signal ADSC* is activated, causing the first address A
0
to be registered into the SRAM. The registered address A
0
is then presented to the memory array (not shown) of the SRAM at time t
1
, and the data D
0
specified by the address A
0
is output from the array at time t
2
and from the SRAM at time t
3
. Next, an internally-generated burst address A
0
+1 is presented to the memory array at time t
4
, causing the array to output the data D
0
+1 specified by the address A
0
+1 at the same time. The data D
0
+1 is then output from the SRAM at time t
5
. Thereafter, internally-generated burst addresses A
0
+2 and A
0
+3, respectively, are presented to the memory array at times t
6
and t
8
, respectively, causing the array to output the data D
0
+2 and D
0
+3 specified by the addresses A
0
+2 and A
0
+3, respectively, at the same times. The data D
0
+2 and D
0
+3 are then output from the SRAM at times t
7
and t
10
, respectively. Before the data D
0
+3 is output from the SRAM at time t
10
, the address register signal ADSC* is activated again at time t
9
, causing the second address A
1
to be registered into the SRAM at the same time. The read operation
12
then proceeds in the same manner as the read operation
10
.
It should be noted that because the address A
0
+3 is still being presented to the array when the second address A
1
is registered at time t
9
, the idle cycle
14
is necessary to provide sufficient recovery time from the operation performed at A
0
+3.
Write operations in modern burst-oriented SRAM devices are also not as fast as is desirable. For example, as shown in
FIG. 2
, sequential write operations
20
and
22
(only a portion of write operation
22
is shown in
FIG. 2
) in a conventional burst-oriented SRAM (not shown) are separated by a recovery period
24
, which adds to the total time it takes to perform the write operations
20
and
22
.
More specifically, the first write operation
20
is initiated at time t
0
when the address register signal ADSC* is activated, causing the first address A
0
to be registered into the SRAM. The registered address A
0
is then presented to the memory array (not shown) of the SRAM at time t
1
, and the first data D
0
is registered into the SRAM at time t
2
. Next, the registered data D
0
is written into the array at time t
3
at the location specified by the address A
0
, and the data D
0
+1 is registered into the SRAM at time t
4
. Thereafter, internally-generated burst addresses A
0
+1 and A
0
+2 are presented to the memory array at times t
5
and t
7
, respectively, the data D
0
+2 and D
0
+3 is registered into the SRAM at times t
6
and t
8
, respectively, and the data D
0
+1 and D
0
+2 is written into the array at the locations specified by the addresses A
0
+1 and A
0
+2, respectively, at times t
5
and t
7
. An internally-generated burst address A
0
+3 is then presented to the memory array at time t
9
, causing the data D
0
+3 to be written into the array at the location specified by the address A
0
+3 at the same time. Next, the address register signal ADSC* is activated again at time t
10
, causing the second address A
1
to be registered into the SRAM. The second write operation
22
then proceeds in the same manner as the first write operation
20
after the recovery period
24
has passed.
Accordingly, because conventional synchronous SRAMs include idle cycles during read and write operations that limit the bandwidth of such SRAMs, there is a need in the art for a device and method that reduces the number of idle cycles necessary in read and write operations of semiconductor memory devices, such as sequential SRAMs, thereby further accelerating read and write operations in such devices.
BRIEF SUMMARY OF THE INVENTION
In one embodiment of this invention, a memory operation (e.g., a read or write operation) is performed in a semiconductor memory (e.g., a synchronous, burst-oriented Static Random Access Memory (SRAM)) by selecting an N-bit wide row of the semiconductor memory. Then, a number (X) of data portions of N/X bits each are simultaneously transferred between the selected row and N-bit wide temporary storage that is in communication with the selected row.
In another embodiment, N data bits are read from a semiconductor memory by first selecting a row of the semiconductor memory in accordance with an externally supplied address. N data bits stored in the selected row are then simultaneously accessed and temporarily stored (e.g., in N latched sense amplifiers). A portion of the temporarily stored N data bits are then selected in accordance with the externally supplied address and read out of the semiconductor memory. Next, one or more internal burst addresses are generated from the externally supplied address and, for each internal burst address generated, another portion of the temporarily stored N data bits is selected in accordance with the internal burst address and read out of the semiconductor memory.
In still another embodiment, N data bits are written into a semiconductor memory. The N data bits are first received in a plurality of sequential portions, and one of the sequential portions of the N data bits is temporarily stored in accordance with an externally supplied address. Also, one or more internal burst addresses are generated from the externally supplied address and, for each internal burst address generated, another one of the sequential portions of the N data bits is temporarily stored in accordance with the internal burst address. A row of the semiconductor memory is then selected in accordance with the externally supplied address, and the temporarily stored sequential portions of the N data bits are simultaneously written into the selected row.
In yet another embodiment of this invention, a burst-oriented SRAM having a burst length of X includes a memory array having a plurality of N-bit wide rows. Storage circuitry temporarily stores N bits, and buffer circuitry buffers X sequential data portions of N/X bits each. Multiplexing circuitry between the storage circuitry and the buffer circuitry sequentially transfers the X sequential data portions between the storage circuitry and the buffer circuitry,
Pawlowski Joseph T.
Wilford John R.
Micro)n Technology, Inc.
Nguyen Tuan T.
TraskBritt
LandOfFree
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