Circuit and method for reducing lock-in time in phase-locked and

Details Circuit and method for reducing lock-in time in phase-locked and Circuit and method for reducing lock-in time in phase-locked and

1997-03-19

2000-02-29

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 1A, 327156, 327159, H03L 700

Patent

active

06031429&

ABSTRACT:
Method and circuit aspects for improving lock-in time following power-up in a phase-locked loop are provided. The circuit and method for providing same includes a phase-locked loop, the phase-locked loop comprising a low pass filter, and a pulse generation circuit coupled to the low pass filter. The pulse generation circuit provides a control pulse of predetermined duration to increase a voltage across the low pass filter and reduce lock-in time in the phase-locked loop following power-up. The pulse generation circuit further includes a plurality of logic gates, the plurality of logic gates including a plurality of inverters coupled to a NAND gate.

REFERENCES:
patent: 5223755 (1993-06-01), Richley
patent: 5523726 (1996-06-01), Assar et al.

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