Circuit and method for reducing jitter in a PLL of high...

Details Circuit and method for reducing jitter in a PLL of high... Circuit and method for reducing jitter in a PLL of high...

2006-05-09

2006-05-09

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C331S185000

Reexamination Certificate

active

07042277

ABSTRACT:
Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

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