Circuit and method for reducing fatigue in ferroelectric...

Details Circuit and method for reducing fatigue in ferroelectric... Circuit and method for reducing fatigue in ferroelectric...

2006-07-18

2006-07-18

Phan, Trong (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S145000, C365S185080

Reexamination Certificate

active

07079408

ABSTRACT:
A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit604. The first address820and the first data word842are stored in a volatile memory circuit602. A first external address608is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus610when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.

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Ali Sheikholeslami,Ferroelectric Memory Design(FeRAM 101), ISSCC 2002 Tutorial (Feb. 3, 2002).

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