Circuit and method for reducing direct current biases

Details Circuit and method for reducing direct current biases Circuit and method for reducing direct current biases

2007-06-05

2007-06-05

Orgad, Edan (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Noise or interference elimination

C455S283000, C455S284000, C455S295000, C455S301000, C455S303000, C455S305000, C375S317000, C375S319000

Reexamination Certificate

active

10990400

ABSTRACT:
A method is provided for reducing a DC bias in a receiver. This method includes isolating a second circuit portion from a first circuit portion (535) and determining a second DC bias correction value for the second circuit portion that will eliminate a second DC bias at the isolated second circuit portion (540). The second circuit portion is then connected to the first circuit portion (550) and a bias-maximizing code word is generated at the first circuitry (505). A first DC bias correction value is then determined that will eliminate a first DC bias at the first circuit portion (555). The bias-maximizing code word is formed such that: a first integrated value of a first half of the bias-maximizing code word has a positive value, and a second integrated value of a second half of the bias-maximizing code word over half of the code word length has a negative value.

REFERENCES:
patent: 4142110 (1979-02-01), Weber
patent: 7072427 (2006-07-01), Rawlins et al.
patent: 2002/0160734 (2002-10-01), Li et al.
patent: 2003/0224752 (2003-12-01), Rawlins et al.
patent: 2004/0002321 (2004-01-01), Sorrells et al.
patent: 2005/0143042 (2005-06-01), Sorrells et al.
patent: 2005/0225395 (2005-10-01), Gao et al.
patent: 2007/0010223 (2007-01-01), Demir et al.

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