Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-10-07
2001-06-26
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S563000
Reexamination Certificate
active
06252437
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to electronic circuitry and, more specifically, to a circuit and method for reducing a propagation delay associated with a comparator and a comparator employing the same.
BACKGROUND OF THE INVENTION
Technology in the areas of telecommunications and computer systems is continually challenged to provide increased processing speeds with lower power requirements. Lap top computer systems provide a particular challenge in this respect in that higher processing speeds and lower power requirements form the basis for a competitive advantage for a supplier. Users of personal computer systems, especially lap top computer users, are also demanding increased functionality in addition to the enhanced speed and power requirements. One such demand is the ability to reliably connect to a telephone line to transmit and receive data at high data speeds. For example, since the wide use of the Internet, consumers are demanding that modems connect at the same high data speed each time they connect to the Internet.
Personal computer systems use very fast internal clock signals, which are approaching the realm of one gigahertz, to achieve the fast processing rates. The fast clock signals generate considerable electrical noise that is picked up by the various interconnections inside the computer system. The electrical noise typically manifests itself as a common mode signal which can occur on the signal return or “ground” lines causing the lines to “bounce.” If the interfering signals become too large or their effect is not properly accounted for, the interfering signals can cause the operation of the computer system to become intermittent or unreliable. One approach to minimizing the effect of the common mode signals is the use of differential input signals.
A differential input signal consists of two signals wherein the information to be presented is supplied as the signal inverses (i.e., 180 degrees out of phase) or logical complements of each other. A common mode noise signal would add equally to each of the interconnecting lines or traces carrying a differential input signal if the two lines are in close proximity to one another. As long as a circuit can determine the differential input signal, even in the presence of a large common mode noise signal, the circuit will reliably respond to the logic command intended thereby overcoming the common mode noise interference.
A commonly used differential input circuit in computer and telecommunication systems is a comparator circuit. When used in concert with other logic elements having single-ended logic inputs, the differential input comparator accepts a differential input signal and converts the differential logical information to a single-ended logic output signal. The comparators form critical circuit elements in modern computer and telecommunications systems and are, therefore, subject to the same requirements of increased processing speed with lower power usage.
Accordingly, what is needed in the art is a differential comparator that demonstrates satisfactory throughput capability while minimizing the impact on power requirements.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a circuit and method for reducing a propagation delay associated with a comparator and a comparator employing the circuit or method. In one embodiment, the comparator, includes: (1) an input stage that receives a differential input signal and develops therefrom a determinant signal, (2) an output stage, coupled to the input stage, that develops a level shifted single-ended output signal as a function of the determinant signal, and (3) a speed-up circuit, associated with the input stage, that reduces a time period to develop the determinant signal thereby decreasing a propagation delay in developing the level shifted single-ended output signal from the differential input signal. The determinant signal is a scaled representation of the differential input signal wherein the scaling factor is associated with the gain of the input stage.
The present invention therefore introduces, in one aspect, the broad concept of decreasing the propagation delay associated with a comparator by reducing the time period to develop a determinant signal therein. The comparator of the present invention achieves the enhanced performance while conserving the power requirements. In one embodiment of the present invention, the speed-up circuit reduces the time period to develop the determinant signal by shielding a portion of an intrinsic capacitance at a critical node associated with a path between a current source and the speed-up circuit in the comparator. The shielding of the intrinsic capacitance may occur as the output of the comparator transitions to a true condition. Of course, the aforementioned method of employing the speed-up circuit is but one example to achieve the intended purpose.
In one embodiment of the present invention, the input stage includes a current source having at least one semiconductor device. The semiconductor device may be a complementary metal oxide silicon (CMOS) transistor. Those skilled in the pertinent art will recognize, however, that the present invention can be employed with other types of semiconductor devices.
In one embodiment of the present invention, the speed-up circuit includes a pseudo-cascode pull-up current source. Those skilled in the pertinent art will recognize, however, that the speed-up circuit may be embodied in other circuits such as different pull-up current sources.
In one embodiment of the present invention, the speed-up circuit includes at least one switch. The speed-up circuit may cooperate with a current source to isolate the effect of capacitance at the output of the current source. In another embodiment of the present invention, the speed-up circuit may include more than one switch.
In one embodiment of the present invention, the output stage includes at least one inverter circuit. In another embodiment of the present invention, the output stage includes more than one inverter circuit and may include other types of circuits as the specific application dictates.
In one embodiment of the present invention, the output stage includes a feedback circuit. In yet another related, but alternative embodiment, the feedback circuit reduces a power dissipation in the output stage in developing the level shifted single-ended output signal. In still another related, but alternative embodiment, the feedback circuit reduces the power dissipation by decreasing a current flow through the output stage.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5898323 (1999-04-01), Suda
patent: 5963062 (1999-10-01), Fujii
patent: 5990708 (1999-11-01), Hu
patent: 6020768 (2000-02-01), Lim
patent: 6124738 (2000-09-01), Iga
patent: 6127854 (2000-10-01), Illegems
Fischer Jonathan H.
Zhu Weilin
Agere Systems Guardian Corp.
Nu Ton My-Trang
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