Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-07-14
2001-02-27
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170
Reexamination Certificate
active
06195286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit and a method for reading a non-volatile memory. More particularly, the invention relates to a reading circuit of a non-volatile memory and an associated reader protocol.
BACKGROUND OF THE INVENTION
It is known that in a conventional non-volatile memory, a random reading method is normally used in which word lines and bit lines are selected randomly and independently. This procedure entails reading times which are the sum of a sequence of events which can be summarized substantially as follows: propagation of the word line and bit line selection paths; precharge activity; a data evaluation interval; and propagation for data transfer to the output buffer and transition time of the buffer.
The total reading time, given by the sum of the times of the individual operations listed above, depends not only on the dimensions and architecture of the memory but also on the type of device that is present in the memory, i.e., on the technology that is used. The advantages of the conventional architecture are that it is simple (a minimal number of memory structures), it allows easy timing (because all reading cycles are equal), it provides maximum efficiency for redundancy structures, and it has significantly low consumption because the number of current-consuming circuits is kept to the lowest possible value.
However, the limitations of the conventional architecture reside in the reading speed, which is very important in large memories. One approach for improving the reading speed is the use of “page mode” reading, in which a plurality of words in parallel, for example eight, are read in a first cycle. Then, the content of the reading operation is stored in a suitable register and the portion of the register that relates to the selected word within the packet of read words is displayed externally. In this manner it is possible to scan the words contained in the packet of read words in a significantly shorter time than with random reading. However, the first reading cycle continues to be dependent on the time of a random selection.
In any case, page-mode reading is affected by the following drawbacks: a large number of reader circuits (e.g., if eight words of eight bits each are read in parallel, sixty-four sense amplifiers are required); high current absorption during parallel reading; the provision of word registers; the provision of register decoding; a reduction in the effectiveness of redundancy structures (one line at a time can be replaced with a redundant line, but in the case of multiple reading, the possibilities of line fault increase, yet there is still only one redundant line available); and the reading protocol entails a double cycle time, random or page.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit and a method for reading a non-volatile memory which allow performance advantages to be achieved, with respect to the conventional reading approach, and yet are simplified with respect to the page-mode approach. Thus, an object of the present invention is to provide a circuit and a method for reading a non-volatile memory which keep the number of structures of the memory to a minimum.
Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which do not require the reduction of the effectiveness of redundancy or the implementation of additional reader and decoder registers. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which avoid additional current consumption. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which are highly reliable, relatively easy to provide and at competitive costs.
These objects and others which will become apparent hereinafter are achieved by a method for reading a non-volatile memory including the steps of: providing a first random memory reading cycle; performing, at the end of the random reading cycle, a collective page precharge; subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
Further characteristics and advantages of the invention will become apparent from the description of preferred but not exclusive embodiments of the circuit and of the method according to the invention, illustrated only by way of non-limitative examples in the accompanying drawings, wherein:
FIG. 1
is a schematic view of a first embodiment of an organizational structure of a non-volatile memory according to the present invention;
FIG. 2
is a schematic view of a second embodiment of an organizational structure of a non-volatile memory according to the present invention;
FIG. 3
is a chart of the reading timings of a non-volatile memory according to a known reading cycle, which points out the regularity of the timing events (reading cycles), as in the prior art;
FIG. 4
is a chart of the read timings of a non-volatile memory according to a reading cycle provided with the circuit and the method according to the present invention; and
FIG. 5
is a chart of the reading timings of a non-volatile memory provided according to the invention and with continuous page changing after an initial random cycle.
REFERENCES:
patent: 5748538 (1998-05-01), Lee et al.
patent: 5761132 (1998-06-01), Kim
patent: 5940321 (1999-08-01), Takeuchi et al.
patent: 0 372 873 A3 (1989-12-01), None
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Phan Trong
STMicroelectronics S.r.l.
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