Circuit and method for rapid calculation of quotients and square

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364767, G06F 752

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active

059109106

ABSTRACT:
A circuit and method for accelerating the division algorithm and square root operations relating to integers or floating-point numbers. Minimization of the number of gate delays per quotient digit generated is achieved through the use of triply-redundant representation of the partial remainder and a fully-overlapped quotient digit prediction scheme suitable for logic implementation. Moreover, faster quotient digit selection is achieved by prescaling the dividend and divisor.

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