Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-12-28
2003-03-04
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185210, C365S185330
Reexamination Certificate
active
06529405
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 87293/2000 filed Dec. 30, 2000, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit and method for programming and reading a multi-level flash memory, which provide sufficient intervals between threshold voltage distributions and improve the level sensing speed of the flash memory.
2. Discussion of the Related Art
A non-volatile memory maintains its stored data even when its power source disappears. EPPROM or EEPROM is a non-volatile memory that does not require a refresh operation, as compared to SRAMs. EEPROM that erases data stored in its memory cells by block units, instead of byte units, is known as a flash memory.
A conventional flash memory includes a plurality of memory cells for storing data. Each memory cell generally includes a transistor having a floating gate. To store data in the memory cells of a flash memory, i.e., to program the flash memory, certain amounts of electrons are injected into the floating gates of the memory cells to set the threshold levels of the memory cells to desired levels. Different threshold levels set in the memory cells represent different data. Generally, the threshold levels of the memory cells are detected and compared with predetermined reference levels provided by reference cells, so as to determine the different levels of the memory cells. For instance, in a memory cell having two levels (i.e., it stores one-bit information), If the memory cell has a first threshold level, it may represent a storage of “0” for the one bit, whereas if the memory cell has a second threshold level, it may represent a storage of “1” for the bit. In this manner, each memory cell of the flash memory can store multiple levels corresponding to multiple bit information.
To erase the flash memory, the electrons injected in the floating gates are extracted from the floating gates to reduce the threshold voltages of the cell transistors to desired levels.
There exist different conventional methods for programming and reading a flash memory. For example, the EEPROM flash memory can be programmed by repeating short durations of programming and verifying operations until the desired threshold levels have been set for the memory cells. In another example, the flash memory can be programmed by applying a long program pulse to the memory cells until the memory cells are programmed with the desired threshold levels and then releasing all programming conditions once the memory cells are programmed.
A method of reading a multi-level flash memory according to a related art, involves applying one fixed voltage to the control gates of memory cells and reference cells and simultaneously comparing the threshold voltage of the memory cells with different reference voltages using a sensing amplifier. Here, the sensing amplifier includes an X number of comparators wherein X=[(the number of levels)−1]. The comparators are used to determine the levels of the memory cells.
FIG. 1A
is a diagram of a related art circuit in which the above-described method of reading the flash memory can be implemented. As shown, this circuit is constructed with a memory cell
10
for storing two-bit data (four levels), a drain bias unit
12
for supplying a drain of the memory cell
10
with a power source voltage Vdd, a reference cell block
14
for producing three kinds of reference currents ref
1
, ref
2
, and ref
3
, three comparators
16
,
18
, and
20
for comparing respectively the reference currents ref
1
, ref
2
, and ref
3
to the drain current of the memory cell
10
, and a decoding unit
22
for outputting 2-bit data made of MSB (most significant bit) and LSB (least significant bit) by decoding outputs X
1
, X
2
, and X
3
of the comparators
16
,
18
, and
20
according to known techniques.
In the circuit of
FIG. 1A
, a fixed voltage is applied to the control gates of the memory cell
10
and reference cells in the reference cell block
14
. As a result, a drain current or cell current “Icell” of the memory cell
10
is applied to the comparators
16
,
18
and
20
, and at the same time, the reference currents ref
1
, ref
2
, and ref
3
having different ranges are applied simultaneously to the comparators
16
,
18
, and
20
, respectively. The comparators
16
,
18
, and
20
compare the cell current Icell with the corresponding reference current to output comparison results X
1
, X
2
and X
3
. The decoding unit
22
outputs MSB and LSB (2 bit/four levels) in accordance with the comparison results X
1
, X
2
, and X
3
. For example, if the comparison results indicate that the cell current Icell of the memory cell
10
is at a level
4
, then the decoding unit
22
may output (
1
,
1
) as MSB and LSB.
FIG. 1B
is a graph showing threshold voltage distributions of the circuit of
FIG. 1A
according to a related art. As shown in
FIG. 1B
, the memory cell
10
can store two-bits (MSB and LSB) of information. That is, the memory cell
10
has four possible levels (
0
,
0
), (
0
,
1
), (
1
,
0
) and (
1
,
1
), which are detected by using the reference currents ref
1
, ref
2
and ref
3
. The reference currents ref
1
, ref
2
, and ref
3
are distributed in accordance with a distribution size of a threshold voltage Vt of the memory cell
10
, so as to fall between two of the possible threshold voltage distributions of the circuit.
Despite the advantage that a particular level of a multi-level memory cell can be sensed by a single operation using the multiple comparators
16
,
18
and
20
, the circuit of
FIG. 1A
suffers from the following problems. In the circuit of
FIG. 1A
, a large number of voltage distributions must be made within a limited voltage range or threshold voltage window. For example, as shown in
FIGS. 1B and 1C
, a four-level (2 bit) flash memory requires four different threshold voltage distributions for the memory cell, and three different reference currents/voltages therebetween, a total of seven voltage distributions within an allotted threshold voltage window. In another example, a 4-bit flash memory requires 16 threshold voltage distributions for the memory cells and 15 reference current cells/voltages, a total of thirty-one (31) voltage distributions within an allotted threshold voltage window. This crowds the voltage threshold window and causes errors in level detections. Particularly, as the number of bits representing the respective levels of the flash memory increases, this decreases significantly a margin for establishing the threshold voltage distributions within the threshold voltage window, rendering the problem much more serious for high-bit flash memories. In this regard, it becomes extremely difficult and ineffective to use the above-described conventional method to read a memory cell stored with over 3 bits of information.
FIG. 2A
is a diagram of a circuit for programming and reading a multi-level flash memory according to another related art and
FIG. 2B
shows an example of a graph of threshold voltage distributions for the circuit of FIG.
2
A. As shown, this circuit is constructed with a memory cell
30
for storing data, a drain bias unit
32
for supplying a drain of the memory cell
30
with a power source voltage Vdd, a reference cell block
34
for producing a reference voltage Vref, a single comparator
36
for comparing the reference voltage Vref to a drain voltage of the memory cell
30
, and a decoding unit
38
for outputting two bits MSB and LSB of data by decoding an output X
4
of the comparator
36
.
In the circuit of
FIG. 2A
, a voltage Vgs is applied to the control gates of the memory cell
30
and a reference cell of the reference cell block
34
, wherein the voltage Vgs is increased (or decreased) sequentially by three steps to voltage V
1
, V
2
, and then V
3
, as shown in FIG.
2
C. As a result, the reference voltage Vref of varying range is applied one at a time to the comparator
36
depending on the voltage V
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Lam David
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