Circuit and method for preventing runaway in a phase lock loop

Details Circuit and method for preventing runaway in a phase lock loop Circuit and method for preventing runaway in a phase lock loop

1999-10-27

2002-04-09

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Amplitude compensation

C331S017000, C331S00100A, C327S156000, C327S159000

Reexamination Certificate

active

06369660

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to phase lock loop circuits generally and, more particularly, to a circuit and method for preventing a runaway condition in a phase lock loop circuit.
BACKGROUND OF THE INVENTION
Voltage controlled oscillators (VCOs) are used in phase lock loops (PLLs) to generate clocks having particular frequencies. PLLs are generally considered clock multipliers. For example, an input reference clock having a frequency of 10 Mhz can be multiplied by the PLL to yield an output clock signal having a frequency of 100 Mhz. Ideally, this clock multiplication would result in an output clock which is in perfect phase/frequency with the reference clock. However, a condition generally referred to as VCO “runaway” is a condition that can occur when the output of the VCO is running at such high speed that the PLL (typically the counters in the PLL) are not capable of operating at a sufficient speed to keep up with the VCO output clock signal. This condition can (and does) occur during power up and initial lock acquisition.
Referring to
FIG. 1
, a circuit
10
illustrating a conventional phase lock loop circuit is shown. The circuit
10
generally comprises a phase frequency detector (PFD)
12
, a loop filter
14
, a voltage controlled oscillator (VCO)
16
and a divider
18
. The VCO
16
presents a signal (i.e., VCO_CLK) to the divider
18
. The divider
18
presents a feedback signal to the PFD
12
. The PFD
12
also receives a reference clock (i.e., CLK). The difference in frequency between the reference clock CLK and the feedback signal is used to generate two control signals (i.e., PumpUP and PumpDN) that are presented to the loop filter
14
. The loop filter
14
presents a voltage control signal to the VCO
16
in response to the control signals PumpUP and PumpDN. During normal operating conditions, the reference clock CLK is generally synchronized with the feedback signal. Such a synchronization is shown by the block
20
.
An example of the runaway condition can be described using an example of an 200 Mhz PLL
10
having a divider implementing divide-by-20 feedback counters and an 10 Mhz reference clock CLK. When the PLL
10
is initially powered on, the control nodes (i.e., the input) of the VCO
16
are set to some arbitrary high voltage. In the example of a wide frequency range VCO
16
, oscillations beyond a normal operating range could result. If the feedback counters of the divider
18
are designed to run at 200 Mhz or below (either due to current consumption or structural limitations) the output of the feedback counter
18
may be unpredictable. The divider
18
is likely to generate an output signal having a low frequency related to the underlying noise factors (perhaps in the 1 Mhz range). Since the reference clock CLK presented to the PFD
12
is set to 10 Mhz and the feedback signal is now oscillating at only 1 Mhz, the PFD
12
will generate predominately PumpUP control signals to the loop filter
14
. As a result, a further increase in the control nodes to the VCO
16
will occur, which results in the VCO
16
presenting the output clock signal VCO_CLK running at an even faster frequency.
In addition, the runaway condition can occur in the VCO
16
when the output clock signal VCO_CLK has a frequency that increases to the point where the feedback counters of the divider
18
fail. Alternately, in a case where the feedback from the VCO
16
is derived outside of the chip, a high load can “kill” the frequency of the feedback signal presented to the PFD, which causes a sequence of PumpUP control signals to be presented to the VCO
16
.
The ultimate effects of a VCO runaway condition are dramatic. When implemented in a typical PLL system (such as that shown in FIG.
1
), a “lock-up” condition can occur which requires a hard reset to allow the VCO
16
to resume normal operation.
One conventional approach that may be used to reduce the effect of a VCO runaway condition may be to build a feedback divider
18
(and the associated counters and logic) that can always keep up with the operating frequency of the VCO
16
. However, to prevent the runaway condition, such logic and counters can be required to run at very fast speeds, which can draw high amounts of current. Such a high speed, high current device may be impossible to implement if the VCO
16
is a CML derivative and the counters are implemented in CMOS technology. Additionally, such a solution continues to emphasize these drawbacks as operating frequencies continue to increase.
Another conventional approach is to place a voltage clamp on the control node (i.e., the input) of the VCO
16
that can track the process corners of the particular technology in which the PLL
10
is implemented. However, a voltage clamp that can function over a wide variety of process corners can be difficult to design. If the clamp does not track the process corners adequately, a lock-up condition can still occur. As the overall frequency of oscillation of the PLL
10
increases, the difficulty in designing a voltage clamp that tracks the process corners increases.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.
The objects, features and advantages of the present invention include providing a circuit and method for preventing runaway in a phase lock loop that may (i) provide a more robust device, (ii) provide better reliability, (iii) require little added die area, (iv) save board level component cost, (v) save design time, and/or (vi) eliminate need for external components by allowing implementation on the same chip as the PLL.


REFERENCES:
patent: 4484152 (1984-11-01), Lee
patent: 4996444 (1991-02-01), Thomas et al.
patent: 5694087 (1997-12-01), Ferraiolo et al.
patent: 5828253 (1998-10-01), Murayama
Nathan Y. Moyal et al., Circuits, Architectures and Methods for Detecting and Correcting Excess Oscillator Frequencies, Serial No. 09/159,908, filed Sep. 24, 1998, now U.S. Patent 6,140,880.
Richard Chou et al., Method, Architecture and Circuit for Controlling and/or Operating an Oscillator, Serial No. 09/320,057, filed May 22, 1999, now U.S. Patent 6177843.

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