Circuit and method for predicting dead time

Details Circuit and method for predicting dead time Circuit and method for predicting dead time

2006-05-30

2006-05-30

Nguyen, Vincent Q. (Department: 2858)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

C324S433000, C320S149000

Reexamination Certificate

active

07053632

ABSTRACT:
A circuit for predicting the dead time is provided. The circuit includes a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

REFERENCES:
patent: 3621359 (1971-11-01), Schnegg
patent: 5896025 (1999-04-01), Yamaguchi et al.

Affiliated with

Also associated with

Rating

Circuit and method for predicting dead time does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for predicting dead time, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for predicting dead time will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3588397