Circuit and method for performing integer power operations

Details Circuit and method for performing integer power operations Circuit and method for performing integer power operations

1991-12-13

1993-03-16

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

051950529

ABSTRACT:
An arithmetic circuit for performing an integer power operation having a first register that is initially stored with integer power data, a second register stored with base data and a multiplier for multiplying the second register contents with a third register. A control circuit is provided for iteratively shifting the first register and for each iteration (1) selectively multiplying, according to data shifted from said first register, the second register data by the third register data and storing the results in the third register, and (2) multiplying the second register data by itself and storing the results back into the second register. These iterative steps are continued until the remaining data in the first register indicates that the arithmetic operation is complete, whereupon a completion signal is provided.

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patent: 4410956 (1983-10-01), Yoshida
patent: 4758975 (1988-07-01), Omoda et al.
patent: 4787056 (1988-11-01), Dieterich
IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, pp. 328-330, "Efficient Arithmetic Apparatus and Method".
IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, pp. 171-173, "Exponential by Sequential Squaring".
IBM Technical Disclosure Bulletin, vol. 32, No. 7, Dec. 1989, pp. 222-223, "16-Bit Floating-Point Math in an 8-Bit Microprocessor".
IBM Technical Disclosure Bulletin, vol. 33, No. 1B, Jun. 1990, pp. 312-313, "Exponent Shift Count Logic".

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