Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2007-05-15
2007-05-15
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
C365S194000, C365S233100
Reexamination Certificate
active
11482268
ABSTRACT:
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.
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Gomm Tyler
Smith Scott
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Tuan T.
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