Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1997-12-18
2000-07-18
Williams, Howard L.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
H03M 700
Patent
active
060913487
ABSTRACT:
A digital delay line, comprising adjustable digital delay elements, receives and buffers an incoming bit stream by repeatedly delaying bits of the bit stream for a specific period of time. The outputs of selected adjustable digital delay elements are tapped for providing a specific pattern of bits in parallel to a function block. The function block operates on the parallel bits on-the-fly to detect and substitute bits for decoding, descrambling, decrypting, or performing any other such function.
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Advanced Micro Devices , Inc.
Williams Howard L.
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