Circuit and method for on-chip jitter measurement

Details Circuit and method for on-chip jitter measurement Circuit and method for on-chip jitter measurement

2006-06-19

2008-03-04

Nguyen, Vincent Q. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076110, C324S765010, C327S158000

Reexamination Certificate

active

07339364

ABSTRACT:
An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

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