Circuit and method for multilevel signal decoding, descrambling,

Pulse or digital communications – Multilevel

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375289, 375340, 375287, 329347, 327 75, 327262, 327270, H04L 2534

Patent

active

060786272

ABSTRACT:
At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

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