Pulse or digital communications – Pulse width modulation
Reexamination Certificate
1998-11-19
2001-10-30
Pham, Chi (Department: 2631)
Pulse or digital communications
Pulse width modulation
C332S109000
Reexamination Certificate
active
06310913
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a pulse width modulation (PWM) circuit and method, and more particularly to a PWM circuit and method applicable to D/A converters for converting a digital signal to an analog signal, communication circuits, and control circuits such as an inverter for driving a power device such as a motor.
BACKGROUND ART
First Prior Art
In a first conventional analog type PWM circuit, a PWM signal is obtained by comparing an isosceles triangle reference signal and a signal to be modulated (referred to as a modulation signal, hereinafter) with a comparator. In this case there is no phase change of the PWM signal dependent on the magnitude of the modulation signal.
On the other hand, there is a method for realizing a digital type PWM circuit. As shown in
FIG. 2A
, the sawtooth waveform C in the form of a right-angled triangle generated by a ring counter is used as a reference signal, and this reference signal and modulation signal D are input to a magnitude comparator, in which the magnitudes of both signals are compared with each other. The comparison result of the magnitude comparator is used as a PWM signal (PWM
1
). This digital type method is easily obtained from the analog type method. This digital type method has the excellent advantage that it requires only a magnitude comparator when multi-channel PWM is realized. This method also has the feature that if the cycle to update modulation data is equal to that of the ring counter or any integral multiple of the ring counter cycle, the modulation characteristic will become ideally linear and therefore the resolution and carrier cycle of the PWM signal obtained will be equal to those of the ring counter.
Second Prior Art
On the other hand, for the specification of the PWM required of A/D converters or motor control, there is a demand to make the carrier frequency higher than the updating frequency of modulation data without degrading PWM resolution. A method for meeting this demand has been proposed in Japanese Patent Application Laying-Open No. 3-76311 filed by the same applicant as this patent application.
Another method for converting modulation data expressed in two's complement to a PWM signal by simple constitution has been proposed in Japanese Patent Application Laying-Open No. 3-76312 filed by the same applicant as this patent application.
Furthermore, other methods to the present invention have been proposed in Japanese Patent Application Laying-Open Nos. 1-36118, 1-37124, 2-219321, 4-295280, 4-318469, 6-53794, 6-311040, and 8-88566.
Regarding the First Prior Art
In the method for realizing a digital type PWM circuit, mentioned in the first prior art, the phase of the PWM signal (PWM
1
) changes in dependence on the magnitude (i.e., the phase of the leading edge of each PWM signal does not change, but if the center of the high level portion of each PWM signal is thought of as the phase, the phase changes). In order to prevent a change in the phase, an up-down counter for counting up or down clock pulses and a few control circuits are employed in generating a reference signal. Clock pulses are counted down in the first half cycle of the reference signal and counted up in the second half cycle, whereby a triangle waveform in the form of an isosceles triangle is generated. This triangle waveform may be employed as the reference signal.
The aforementioned method for preventing the phase change in the digital method, however, has the following problems.
(1) The upper limit of the resolution of the digital PWM per cycle is theoretically the number of clock pulses per cycle, but the resolution will be reduced by one bit as compared with that of the above-mentioned sawtooth reference signal. That is, for instance, in the case of a 4-bit reference signal, a sawtooth waveform signal has 16 levels consisting of levels 0 to 15, as shown in
FIG. 4A
(however, in this case the above-mentioned phase change will take place). If this sawtooth waveform signal is applied to the above-mentioned method for preventing the phase change in the digital method, two cycle times will be required to obtain 16 levels in each of the down-counting and up-counting. On the other hand, since one cycle has 16 clock pulses, only 8 levels, 0, 2, 4, 6, 8, 10, 12, and 14, are obtained in both the down-counting and the up-counting (i.e., the resolution is reduced by one bit). (2) The circuitry is complicated.
Regarding the Second Prior Art
Even in each method mentioned in the second prior art, as with
FIG. 2A
, the phase of the PWM signal changes in dependence on the magnitude. That is, the phase of the leading edge of each PWM signal does not change, but if the center of the high level portion of each PWM signal is thought of as the phase, the phase changes.
If ideal modulation is to be performed with the digital type PWM circuit mentioned in the second prior art, the carrier cycle must be equal to the clock cycle raised to second power. However, the required clock frequency of the PWM circuit does not always match with those of the peripheral circuits. Hence, the PWM circuit requires a phase-locked loop (PLL) or an exclusive clock generator to ensure a required clock frequency. Furthermore, the aforementioned conventional methods cannot meet a demand to enhance high-speed controllability, because the cycle to update modulation data is the same as the carrier cycle even when the updating cycle i s shortest.
Accordingly, it is an object of the present invention to provide a PWM circuit and method which has overcome the aforementioned problems.
Another object of the present invention is to provide a PWM circuit and method which can be realized with simple circuitry.
Still another object of the present invention is to provide a PWM circuit and method which has no phase change and has a high resolution and can gradually increase the carrier frequency arbitrarily at the low pulsating component.
A further object of the present invention is to provide a PWM circuit and method which can generate a good PWM signal even when the carrier cycle is not equal to the clock cycle raised to second power, and therefore, the object is to provide a PWM circuit and method which requires no additional exclusive clock pulse.
A still further object of the present invention is to provide a PWM circuit and method which can be realized inexpensively with a little analog waveform degradation in the case where the PWM circuit is applied to a D/A converter and a little controllability degradation in the case where the PWM circuit is applied to power control.
A still further object of the present invention is to provide a PWM circuit and method in which modulation of two's complement data and a rounding function can be realized with simple circuitry by making unnecessary a 1-adder which was required in prior art, and therefore, the object is to provide a PWM circuit and method which is capable of eliminating the problems that an offset of ½ LSB occurs when a lower bit is omitted instead of being rounded by a rounding function and that a positive 100% duty cycle cannot be output.
DISCLOSURE OF THE INVENTION
To achieve the aforementioned objects and in accordance with one aspect of the present invention, there is provided a pulse width modulation circuit comprising:
In a first aspect of the present invention, there is provided a pulse width modulation circuit comprising:
signal output means for outputting an n-bit signal reiteratedly at a predetermined frequency, the n-bit signal increasing or decreasing stepwise in sequence to a predetermined value;
conversion means for converting the n-bit signal output from the signal output means to a reference signal which reiterates a sequential decrease and a sequential increase or reiterates a sequential increase and a sequential decrease at a frequency which gradually increases the predetermined frequency;
modulation signal output means for outputting modulation signal; and
comparison means for comparing the modulation signal output from the modulation signal output means with the
Asahi Kasei Kabushiki Kaisha
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Pham Chi
Phu Phuong
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