Circuit and method for minimizing recovery time

Details Circuit and method for minimizing recovery time Circuit and method for minimizing recovery time

1998-08-03

2000-11-21

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 1A, 331 18, 331 25, 327142, 327156, 327159, H03L 706, H03L 710, H03L 7089

Patent

active

061508896

ABSTRACT:
A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

REFERENCES:
patent: 4970475 (1990-11-01), Gillig
patent: 5339278 (1994-08-01), Irwin et al.
patent: 5581214 (1996-12-01), Iga
patent: 5592113 (1997-01-01), Quiet et al.

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