Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-02-16
2001-09-18
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S172000, C377S068000
Reexamination Certificate
active
06292041
ABSTRACT:
TECHNICAL FIELD
The invention relates to digital pulse generators. More particularly, the invention relates to methods and apparatus for tracking subthreshold leakage during an active period and generating digital pulses to avoid deleterious effects of subthreshold leakage.
BACKGROUND ART
In certain applications, it is desirable to limit the amount of time a signal is active in CMOS (complementary metal oxide semiconductor) circuits to protect the circuits against various circuit failure modes. One example of a circuit failure mode is a dynamic decay due to subthreshold leakage. A shift register circuit
10
is shown in
FIG. 1
for the purpose of illustrating the deleterious effects of subthreshold leakage. The shift register circuit
10
is shown with only three stages for ease of understanding. Each stage comprises a pass gate
15
, a dynamic storage node
35
,
45
or
55
and an inverter formed by a PFET (P-channel field effect transistor)
20
and an NFET (N-channel field effect transistor)
25
. A shift signal
27
and its inverse, formed by an inverter
28
, are connected to each pass gate
15
. The pass gates
15
store the logic values at the dynamic storage nodes
35
,
45
, and
55
, which are buffered through the inverters to nodes
30
,
40
and
50
. When the shift signal
27
is high, the FETs (field effect transistors) forming the dynamic latch
15
“turn on,” and, as a result, the logic values at the nodes
30
,
40
and
50
pass to nodes
35
,
45
and
55
, respectively. In this way, the logic states stored by the dynamic latches
15
are shifted right each time the shift input signal
27
pulses high. However, when the shift signal
27
is high, subthreshold leakage occurs through the FETs forming the dynamic latches
15
. As used herein, subthreshold leakage is gate current when an FET is conducting. A PFET conducts from source to drain or “turns on” when its gate voltage is low with respect to its source; whereas an NFET turns on when its gate voltage is high with respect to its source. If the shift signal
27
remains high long enough, the subthreshold leakage can be severe enough to cause the latched charge to dissipate. To protect the dynamic latches
15
from failure due to subthreshold leakage requires careful control of the timing of the shift signal
27
. However, given the magnitude of variations present in CMOS circuit manufacturing, a one-size-fits-all solution is not practical.
SUMMARY OF INVENTION
In one respect, the invention is a circuit for processing a pulse for use with a related circuit. The circuit comprises a timer and one or more logic gates. The timer produces an output in a given state if the duration of the pulse reaches a predetermined amount of time. The predetermined amount of time is related to a parameter of the related circuit. The one or more logic gates have an output that is the same as the pulse unless and until the output of the timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state. Preferably, the parameter is a subthreshold leakage rate across an FET.
In another respect, the invention is a method for use with a circuit, such as a shift register, in which leakage can occur at a first rate. The method comprises the step of sensing a condition that prompts leakage to occur in the circuit. In response to the sensing step, the method produces a related leakage at a faster rate than the first rate. The method disables the condition if the related leakage reaches a predetermined level. Preferably, the condition is a pulse.
In yet another respect, the invention is a circuit in which leakage can occur at a first rate. The circuit comprises a means for sensing a condition that prompts leakage to occur in the circuit; a means for producing, in response to the sensing step, a related leakage at a faster rate than the first rate; and a means for disabling the condition if the related leakage reaches a predetermined level.
Certain embodiments of the invention are also capable of realizing the following advantages:
(1) Protecting circuits that use an output signal from failures produced by subthreshold leakage. For example, the dynamic latches in the shift register circuit
10
can be protected by limiting the duration of pulses on the shift signal
27
.
(2) The protection can be self-adapting to the protected circuits, so that an adequate amount of limitation is provided regardless of variations in the manufacturing process.
That is, the protection can track process parameters across manufacturing variations, track the behavior of the circuit being protected (i.e. can use a replica of the circuit prone to failure as the monitor), and allow robust use of circuit types that would otherwise fail due to CMOS manufacturing variations and non-ideal device characteristics.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.
REFERENCES:
patent: 4688018 (1987-08-01), Vaughn
patent: 4797585 (1989-01-01), Segawa et al.
patent: 5202908 (1993-04-01), Hatada
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999.
Hewlett -Packard Company
Zweizig Jeffrey
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