Circuit and method for instruction controllable slewrate of bit

Details Circuit and method for instruction controllable slewrate of bit Circuit and method for instruction controllable slewrate of bit

1996-09-27

1998-07-07

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 49, 36518905, 365227, 326 27, 326 57, 326 58, 327170, 327380, 327381, G11C 800, H03K 190948

Patent

active

057779449

ABSTRACT:
A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

REFERENCES:
patent: 4853896 (1989-08-01), Yamaguchi
patent: 4855623 (1989-08-01), Flaherty
patent: 5471150 (1995-11-01), Jung et al.
patent: 5489862 (1996-02-01), Risinger et al.
patent: 5517129 (1996-05-01), Matsui

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