Static information storage and retrieval – Addressing – Sequential
Reexamination Certificate
2000-05-31
2002-05-14
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Sequential
C365S239000, C365S189120, C365S230060
Reexamination Certificate
active
06388946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to memory arrays in Integrated Circuits (ICs). More particularly, the invention relates to a circuit and method for incrementally selecting and deselecting groups of word lines in a Programmable Read-Only Memory (PROM) array, useful for stress testing Electrically Erasable PROMs (EEPROMs), for example.
2. Description of the Background Art
In IC memory arrays such as PROMs, situations arise in which it is desirable to perform an operation on all locations in the array. One such situation is that of performing a high voltage stress test on each location in an EEPROM array. Another is that of presetting all bit values in the array to a known value, such as zero.
FIG. 1
shows a prior art memory cell
200
for an EEPROM. Such a memory cell typically consists of a single storage transistor
201
. During a read operation, storage transistor
201
either pulls precharged-high bit line BLB to ground GND, or leaves bit line BLB high. Storage transistor
201
is not a typical N-channel transistor, as storage transistor
201
has an extra polysilicon gate called a floating gate (FG). Floating gate FG determines the threshold of storage transistor
201
, based on whether or not there is a charge on floating gate FG. Storage transistor
201
is also controlled by control gate CG, driven by word line WL.
When EEPROM memory cell
200
is not programmed, there is no charge stored on floating gate FG. The threshold of storage transistor
201
is about the same as that of a typical N-channel transistor. Therefore, when word line WL goes high (selecting memory cell
200
), storage transistor
201
is turned on and bit line BLB is pulled low. The sensing circuit for the EEPROM interprets the low value on bit line BLB as a high bit value. Therefore, the unprogrammed value for the EEPROM memory cell is high.
When EEPROM memory cell
200
is programmed, a negative charge is placed on floating gate FG, raising the threshold of storage transistor
201
. (EEPROM storage transistors, and methods for programming them, are well-known in the art of EEPROM design, and therefore are not described herein.) When word line WL goes high, storage transistor
201
does not turn on. Bit line BLB is not pulled low. The sensing circuit for the EEPROM interprets the high value on bit line BLB as a low bit value. Therefore, the programmed value for the EEPROM memory cell is low.
FIG. 2
shows a cross-sectional diagram of storage transistor
201
from EEPROM memory cell
200
of FIG.
1
. Reference to
FIG. 1
shows that one of the two diffusion regions N+ in substrate P is tied to ground GND, and the other to bit line BLB. An oxide layer OX
1
(or other dielectric layers) separates control gate CG from floating gate FG. Oxide layer OX
1
is typically about 200 angstroms thick (or the dielectric equivalent thereof) at point “a” between floating gate FG and control gate CG. An oxide layer OX
2
separates floating gate FG from substrate P and diffusion regions N+. Oxide layer OX
2
is typically about 90-120 Angstroms thick at point “b” between floating gate FG and substrate P. For the unprogrammed cell, if oxide layer OX
2
is too thin or is otherwise defective, oxide layer OX
2
may begin to break down and conduct an electrical charge. For the programmed cell, if oxide layer OX
1
is too thin or is otherwise defective, a similar charge loss may occur. In either case, floating gate FG will not hold a negative charge and storage transistor
201
will cease to operate correctly. Therefore, it is desirable to have the capability of testing the integrity of oxide layers OX
1
and OX
2
at about the voltage level used while programming the EEPROM. Such a test is referred to as a “stress test”. (The term “stress test” as used herein also includes testing the integrity of the oxide layers at a voltage level other than the programming voltage.)
A stress test is typically performed in an EEPROM by selecting a group of one or more word lines in the memory array and applying an overvoltage, suitable for stressing the oxide layers, to the selected word lines. (This overvoltage is typically the voltage level used while programming the EEPROM.) The values in the selected memory cells are then read back to determine whether the storage transistors still function correctly, i.e., whether the oxide layer has maintained its integrity. Another group of word lines is then selected, and the test is repeated. If there are many groups of word lines, the stress test can take an undesirably long time to complete.
It is desirable to perform operations such as stress tests in a short amount of time. Given only this consideration, such an operation could be performed in a single clock cycle on receiving a single initiating signal, by simultaneously selecting all word lines in the EEPROM memory cell array. However, switching all word lines simultaneously might result in a large power surge that could burn out the metal power lines in the IC. It is known that having a large number of simultaneous voltage transitions in an IC is undesirable. For example, to reduce ground bounce caused by the simultaneous switching of large numbers of I/O, the Xilinx XC4000-family devices introduce a deliberate, unclocked skew in the enablement of I/O buffers. (This method is described on page 4-28 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which page is incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying this and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)) It would be desirable to eliminate potentially destructive power surges during EEPROM stress tests, while reducing the amount of time required to perform a stress test on the memory array.
SUMMARY OF THE INVENTION
The invention provides a circuit and method for incrementally selecting and deselecting word lines, thereby enabling the performance of stress tests in EEPROMs without the power surge that would result from simultaneously switching all word lines in the EEPROM memory array. A method is provided for selecting and deselecting word lines in groups of one or more, on receipt of a single initiating signal. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders.
When the stress test initiation signal is received by the control circuit, a state control bit is set high and is clocked into (latched into) the first bit of the shift register (which was initially set to all zeros). The high bit in the first location of the shift register overrides the first group of decoders, selecting the word lines controlled by these decoders. On the next active clock edge, the high bit is loaded into the second bit of the shift register, selecting the second group of word lines, and so on until all word lines in the memory cell array are selected. The stress test is then performed on the entire array simultaneously, reducing the time required to perform the test compared to prior art methods of performing the test on relatively small portions of the array at a time. After the stress test is complete, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.
According to a second aspect of the invention, the circuit and method of the invention can be applied to clearing a memory cell array by incrementally selecting and deselecting word lines.
REFERENCES:
patent: 4597062 (1986-06-01), Asano et al.
patent: 4683555 (1987-07-01), Pinkham
patent: 4796231 (1989-01-01), Pinkham
patent: 4831594 (1989-05-01), Khosrovi et al.
patent: 4985872 (1991-0
Ahrens Michael G.
McGibney Phillip H.
Cartier Lois D.
Casey Michael B.
Ho Hoai V.
Xilinx , Inc.
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