Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
1997-12-18
2001-07-03
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000
Reexamination Certificate
active
06255969
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to digital communications and more particularly to capturing specified bits of a high-speed bit stream.
BACKGROUND ART
In serial based communications systems, data is transmitted serially between network nodes in a bit stream, which comprises a sequence of separate bits, evenly spaced by a bit period. The speed at which a node can process a bit stream in order to examine the information contained therein is determined by, among other factors, the data rate of the bit stream and the bit stream processing latency. The data rate of a bit stream is the inverse of the bit period, and the bit stream processing latency is the delay from the time the bit stream arrives at the node to the time the individual bits are available for inspection.
In conventional systems, the data rate is limited for a variety of reasons. For example, an incoming bit stream is usually stored for processing in a random access memory (RAM) buffer, such as a dynamic RAM (DRAM) buffer and static RAM (SRAM) buffer. Thus, the data rate of a bit stream can be limited by the speed of these memories.
Furthermore, the entire bit stream is typically stored in she RAM buffer before bits of the bit stream may be inspected. Accordingly, the processing latency depends on the size of the incoming bit stream and the rate at which the bit stream can be handled.
As another example, processor intervention may be required to handle the incoming bit stream. The speed of the processor, therefore, can further limit the data rate of the bit stream. Processors can also be relatively costly and require substantial additional hardware and software resources for functions unnecessary to high-speed bit stream capture. If, however, a processor already dedicated for another task is shared, then processing the bit stream reduces the performance of the shared processor.
DISCLOSURE OF THE INVENTION
There exists a need for a circuit and method that can process high-speed data transmissions of bit streams.
There exists a need for a circuit and method that can inspect bits of a bit stream without storing the bits of the bit stream into a RAM buffer.
There exists a need for a circuit and method that can inspect bits of a bit stream without storing the entire bit stream into a RAM buffer.
There exists a need for a circuit and method that can inspect bits of a bit stream without processor intervention.
These and other needs are met by the present invention, in which a bit stream is buffered in a high-speed, digital delay line. This digital delay line is tapped at rar's coins for outputting specified bits of the bit stream in parallel. These specified bits are latched according to a signal generated by a programmable counter so that any pattern of bits at any offset from the start of the bit stream may be observed, before the entire bit stream is received.
According to one aspect of the present invention, a high-speed bit capture circuit comprises a digital delay line for receiving and delaying a bit stream. The digital delay, line includes digital delay elements and taps. Each digital delay element is coupled in series, and each tap is coupled to output of a distinct digital delay element. The circuit also comprises a latch having latch inputs coupled to the taps and a latch control input for latching the parallel data on the latch inputs in response to a latch control signal. A counter counts a prescribed number of bit periods from the start of the bit stream and, when the prescribed number is counted, the counter generates the latch control signal.
Using a digital delay line enables the bit stream to be buffered at a high-speed without RAM or processor intervention. Further, the digital delay line enables bits of the bit stream to be simultaneously available before all of the bit stream has been received.
Another aspect of the present invention is a method of capturing bits from a high-speed bit stream. The method comprises the step of repeatedly delaying, for a bit period, bits from the high-speed bit stream. These bits are tapped to produce parallel data. The method also has the steps of counting a prescribed number of bit stream periods of the high-speed bit stream and latching the parallel data when the prescribed number of bit stream periods is counted. Repeatedly delaying bits of the bit stream enables the bit stream to be buffered at a high-speed without RAM or processor intervention. Further, tapping these bits enables them to be simultaneously available before all of the bit stream has been received.
Additional objects, advantages, and novel features of the present invention will be set forth in part in the detailed description which follows, and in part will become apparent upon examination or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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Advanced Micro Devices , Inc.
Wamsley Patrick
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