Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-05-20
2001-11-20
Lao, Lun-Yi (Department: 2778)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S213000, C345S501000, C348S537000, C348S512000
Reexamination Certificate
active
06320574
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to graphics system, and more specifically to a method and apparatus for recovering a clock signal associated with an analog display data received in a digital display unit (e.g., flat-panel monitor) of a graphics system.
2. Related Art
Digital display units are often used to display images. A flat-panel monitor generally used in lap-top computers is an example of such a digital display unit. A flat-panel monitor typically receives a source image from a graphics controller circuit and displays the source image. Flat-monitors which are being increasingly deployed with desk-top computers is another example of such a digital display unit. The source image is usually received in the form of analog data such as RGB signals well-known in the art.
Digital display devices often need to convert the received analog data into a sequence of pixel data. The need for such a conversion can be appreciated by understanding the general layout of a typical digital display device, which is explained below.
Digital display devices generally include a display screen including a number of horizontal lines.
FIG. 1A
is a block diagram illustrating an example display screen
100
. Each horizontal line (shown as
101
through
106
), in turn, is divided into several discrete points, commonly referred to as pixels. Pixels in the same relative position within a horizontal line may be viewed as forming a vertical lien (shown as dotted line
108
).
The number of horizontal and vertical lines defines the resolution of the corresponding digital display device. Resolutions of typical screens available in the market place include 640×480, 1024×768 etc. At least for the desk-top and lap-top applications, there is a demand for increasingly bigger size display screens. Accordingly, the number of horizontal display lines and the number of pixels within each horizontal line has also been generally increasing.
Thus, to display a source image, the source image is divided into a number of points and each point is displayed on a pixel. Each point may be represented as a pixel data element. Display signals for each pixel in display
100
may be generated using the corresponding display data element. However, as noted earlier, the source image may be received in the form of an analog signal. Thus, the analog data needs to be converted into pixel data for display on a digital display screen.
It is helpful to understand the typical format of the analog data to appreciate the usual conversion process. Generally, each source image is transmitted as a sequence of frames, with each frame including a number of horizontal scan lines. Image is generated on display screen
100
by displaying these successive frames.
Usually, a time reference signal is provided in parallel to divide the analog signal into horizontal scan lines and frames. In the VGA/SVGA environments known in the art, the reference signals include VSYNC and HSYNC. The VSYNC signal indicates the beginning of a frame and the HSYNC signal indicates the beginning of a next source scan line. The relationship between HSYNC and the analog signal data is illustrated further with reference to FIG.
1
B.
Signal
150
of
FIG. 1B
represents an analog display data signal in time domain. Analog signal
150
represents a display image to be generated on display screen
100
. The display signal portions
103
B,
104
B,
105
B etc. represent display data on corresponding horizontal lines
103
A,
104
B, and
105
B respectively. The portions shown as straight lines correspond to a ‘retrace’ period, which signifies the transition to a next horizontal line.
Such transitions are typically indicated by another signal (e.g., HSYNC signal in computer displays). Pulses
103
B,
104
B, and
105
B represent such transitions. Thus, after a transition, the display portion of the signal may be sampled a number of times. The exact number may be proportional to the number of pixels on each horizontal line on display screen
100
. Each display portion is generally sampled the same number of times to generate samples for each pixel.
Thus, to convert the source image received in analog signal form to pixel data suitable for display on a digital display device, each horizontal scan line is converted to a number of pixel data. For such a conversion, each horizontal scan line of analog data is sampled a predetermined number of times. The sampled value is represented as a number, which constitutes a pixel data element.
Each horizontal scan line is typically sampled using a sampling clock signal. That is, the horizontal scan line is usually sampled during each cycle of the sampling clock. Accordingly, the sampling clock is designed to have a frequency such that the display portion of each horizontal scan line is sampled a desired number of times. The desired number can correspond to the number of pixels on each horizontal display line of the display screen. However, the desired number can be different that the number of pixels on each horizontal display line.
Using the sampling scheme described above, each horizontal scan line of a source frame is represented as a number of pixel data. It will be readily appreciated that the relative position of source image points needs to be properly maintained when displaying the source image. Otherwise, some of the lines will appear skewed in relation to the other on the display screen.
To maintain a proper relative position of the source image pixels, the sampling clock may need to be synchronized with the reference signal. That is, assuming for purposes of explanation that HSYNC signal is used as a time reference, the beginning of sampling of analog data for a horizontal display line may need to be synchronized with HSYNC signal pulse. Once such a synchronization is achieved, the following pixels in the same horizontal lines may also be properly aligned with corresponding pixels in other lines.
Phase-locked loop (PLL) circuits implemented using analog components have conventionally been used to achieve such a synchronization.
FIG. 2
is a block diagram of an example PLL circuit
200
which is implemented for such a synchronization. In addition, PLL circuit
200
generates the sampling clock signal also. PLL circuit
200
includes phase detector
210
, filter
220
, amplifier
230
, voltage controlled oscillator (VCO)
240
, and frequency divider
250
. Phase detector
210
compares a time reference (e.g., VSYNC) received on line
102
and sampling clock (more accurately, a signal having a predetermined fraction of the sampling signal) received on line
251
. The two signals are referred to as f
1
and f
2
for brevity.
Phase detector
210
provides on line
212
a signal having a difference of the frequencies of f
1
and f
2
. The signal on line
212
may also include several harmonics of the difference frequency. Filter
220
is generally designed as a low pass filter to eliminate undesirable components. When the frequencies f
1
and f
2
are close, but not equal, line
223
will carry a signal with the difference frequency. VCO
240
is designed to generate a signal with a predetermined frequency. However, the frequency is altered depending on the voltage level received on line
234
.
Amplifier
230
amplifies the signal on line
223
to provide a desired level of voltage on line
234
to modify the frequency of VCO
240
. The voltage level is generated so as to achieve a synchronization of the frequencies f
1
and f
2
. Frequency divider
250
divides the frequency of clock signal received on line
245
by a factor of n. By choosing an appropriate value of n, analog signal data for each horizontal source scan line can be sampled a desired number of times. The signal on line
245
can be used for such a sampling.
However, it is well known in the art, the reference frequency (HSYNC) can vary by a slight value from an average frequency during normal operating conditions. In addition, the reference frequency can drift over a prolonged period of time due to, for exampl
Genesis Microchip Corp.
Lao Lun-Yi
Law Firm of Naren Thappeta
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