Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2009-07-14
2010-10-12
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110, C365S230020, C365S230010, C365S233500, C365S236000
Reexamination Certificate
active
07813215
ABSTRACT:
The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal.
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Hynix / Semiconductor Inc.
Kaminski Jeffri A.
Nguyen Viet Q
Venable LLP
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