Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-06-09
2001-11-20
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S172000, C327S175000
Reexamination Certificate
active
06320434
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic clock generation circuits and methods. More specifically, this invention relates to the use of a method for generating a synchronous clock signal having an improved duty cycle. Such a clock signal may be used in a power factor correction and pulse width modulation controller used in computer display monitors.
BACKGROUND OF THE INVENTION
A PC video display monitor may have several resolutions because of various program requirements. An external synchronization signal is typically used to synchronize these resolutions. Each resolution typically has its own frequency, and the external synchronization signal pulse width may vary depending on its frequency. The frequency range is typically from 30 kHz to 95 kHz.
Power supplies in these display monitors typically use a technique called switched-mode pulse width modulation (“PWM”). Switched-mode PWM synchronizes the switching frequency of the power supply to the display monitor horizontal frequency in order to prevent picture interrupt and to address electromagnetic compatibility/electromagnetic interference (EMC/EMI) issues. Because the horizontal frequency is at least 30 kHz, the switching frequency of the power supply must be set to a frequency somewhat lower than 30 kHz.
With such a variety of frequencies and resolutions, it is difficult for one designing a power supply to use the external synchronization signal to synchronize the PWM controller power supply to the display monitor. One method of synchronizing these devices is to use the turns ratio method to extract from the yoke extra flyback voltage to generate a synchronous signal having an amplitude of about 30V. However, this signal requires a resistor/capacitor network to reduce the voltage level and improve its shape.
Another synchronization method requires a synchronization signal having a clock width of approximately 1 &mgr;s or more and an amplitude exceeding a certain voltage. Such a method is used by SGS-Thomson Microelectronics in its L4981A Power Factor Corrector (“PFC”) integrated circuit. The L4981A requires the external synchronization pulse width to be greater than 800 ns and the signal voltage to be greater than 3.5V. In that scenario, as shown in the timing diagram in
FIG. 1
, a ramp waveform used by the circuit to generate an output clock signal must be kept low until the external synchronization pulse ends, reducing the duty cycle of the output clock. FIG.
1
(
a
) shows the external synchronization signal, SYNC. FIG.
1
(
b
) shows a ramp voltage waveform V
T
which has a slope controlled by an RC time constant. FIG.
1
(
c
) shows the output that is used in the PFC circuit. When SYNC is low (“asynchronous operation”), V
T
ramps up. When V
T
is greater than a preset low threshold voltage
118
, the output is high. As soon as V
T
crosses a preset high threshold voltage
112
, the output goes low, causing V
T
to ramp downward. When V
T
crosses low threshold voltage
118
, the output goes high which reverses the ramp waveform and the cycle repeats. As shown in
FIG. 1
, the output has a duty cycle of approximately 87% between times t
0
and t
1
.
When the SYNC signal begins cycling (“synchronous operation”), a high SYNC signal causes V
T
to ramp downward and the output to go low. However, unlike before when V
T
crossed low threshold voltage
118
and caused the output to go high, when SYNC is high, the output remains low. This prior art synchronization method requires the SYNC signal to be high for at least time interval
124
, between times t
2
and t
4
, and V
T
must be kept low during time interval
130
, from time t
3
to time t
4
, until the SYNC pulse ends. The L4981A requires that time interval
124
be at least 800 ns, and it is typically more. Because of this restriction, the duty cycle of the output may be reduced significantly, to, for example, approximately 60% between times t
4
and t
5
.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for an improved synchronous clock generation circuit and method which allow a synchronization signal to be used without sacrificing duty cycle.
In accordance with the present invention, a circuit for generating a synchronous clock signal includes a synchronization circuit, a ramp and pulse generator, and a clock generator. A synchronization signal and the fed-back synchronous clock signal are inputs to the synchronization circuit which generates a first pulse train. The synchronous clock signal is also fed back to the ramp and pulse generator to generate a second pulse train which includes pulses which are offset in time from the first pulse train pulses. The first and second pulse trains are provided to the clock generator to generate the synchronous clock signal which has a duty cycle that is nearly equal to the duty cycle of an asynchronous clock signal generated in the absence of a synchronization signal.
Preferably, each pulse of the first pulse train generates a positive-going transition for the synchronous clock signal, and each pulse of the second pulse train generates a negative-going transition for the synchronous clock signal.
More specifically, in accordance with one embodiment of the present invention, the synchronization circuit may include an inverter, an S-R latch, and a NOR gate. The synchronization signal is an input to the inverter, and the inverter's output is connected to the R input of the latch. The synchronous clock signal is fed back to the S input of the latch, and the non-inverting output of the latch is connected to one input of the NOR gate. The other input of the NOR gate is the output of the inverter. The output of the NOR gate provides the synchronization circuit pulse train.
The ramp and pulse generator of this embodiment includes a ramp generator and a pulse generator. The ramp generator includes a bipolar junction transistor whose base is connected to the fed-back synchronous clock signal, whose emitter is grounded, and whose collector is connected to the pulse generator. A discharge capacitor is connected between the collector and ground, and a pull-up resistor is connected between the collector and a supply voltage. The pulse generator includes a voltage comparator, the inverting input of which is connected to the collector of the transistor of the ramp generator. The non-inverting input of the voltage comparator is coupled to a reference voltage. The voltage comparator generates the second pulse train. Preferably, the voltage across the capacitor does not have to remain at zero volts until a pulse from the synchronization signal ends.
The clock generator of this embodiment includes an S-R latch. The first pulse train is coupled to the S input of the latch, and the second pulse train is coupled to the R input. The output of the S-R latch is the synchronous clock signal.
In a preferred embodiment of the present invention, an external reference voltage may be input to the circuit.
The synchronous clock signal is preferably used in a second circuit that performs power factor correction and controls pulse width modulation.
Also in accordance with the present invention, a circuit for generating a clock signal capable of having synchronous and asynchronous portions includes a synchronization circuit, a ramp and pulse generator, and a clock generator. A synchronization signal and the fed-back clock signal are inputs to the synchronization circuit which generates a first pulse train. The clock signal is also fed back to the ramp and pulse generator to generate a second pulse train, which includes pulses which are offset in time from the first pulse train pulses, and a third pulse train, which includes pulses earlier in time than those of the second pulse train. The first, second, and third pulse trains are provided to the clock generator to generate the clock signal, as follows. Each pulse of the first pulse train generates a positive-going transition for the synchronous portion of the clock signal, each pulse of the third pulse train generates a positive-going transition for
Chang Jeff
Chu Y. K.
Hsu Lilium
Brady III W. James
Hernandez Pedro P.
Le Dinh T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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