Circuit and method for generating a local clock signal

Details Circuit and method for generating a local clock signal Circuit and method for generating a local clock signal

2002-10-11

2008-03-18

Wang, Ted (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S327000, C375S340000, C375S375000, C327S158000, C327S161000

Reexamination Certificate

active

07346139

ABSTRACT:
A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for receiving an input data signal, (2) (at least) first and second continuously controllable delay lines, coupled to the phase detector, for producing respective first and second candidate local clock signals and (3) delay line selector, coupled to the first and second delay lines, for selecting one of the first and second candidate local clock signals to be the local clock signal based on phase excursions in the input data signal.

REFERENCES:
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patent: 5875219 (1999-02-01), Kim
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patent: 6876239 (2005-04-01), Bell
“A Portable Digital DLL for High-Speed CMOS Interface Circuits” by Bruno W. Garlepp, et al.; IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999; pp. 632-644.
“A Semidigital Dual Delay-Locked Loop” by Stefanos Sidiropoulos; IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997; pp. 1683-1692.

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