Television – Synchronization – Sync generation
Reexamination Certificate
1997-12-31
2001-01-23
Lee, Michael (Department: 2714)
Television
Synchronization
Sync generation
C348S536000, C348S537000, C348S540000, C348S541000, C348S543000, C348S544000, C348S546000, C331S002000, C331S020000, C375S327000, C375S373000, C375S375000, C375S376000
Reexamination Certificate
active
06177959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to television systems, and more specifically to a method and apparatus for generating a clock signal synchronized with time reference signals (e.g, HSYNC) associated with a television signal.
2. Related Art
Phase-lock-loop circuits (PLLs) are often used to generate a clock signal synchronized with an external time reference signal.
FIG. 1
is a block diagram of illustrating an example implementation of a PLL circuit. PLL circuit
100
includes phase detector
110
, charge pump
120
, filter
130
, voltage controlled oscillator (VCO)
140
, and frequency divider
150
. Phase detector
110
compares an external time reference signal received on line
101
and a signal having a fraction (determined by frequency divider
150
) of the frequency of the generated clock signal received on line
151
. The two signals are referred to as f
1
and f
2
for brevity.
Phase detector
110
provides on line
112
a voltage signal indicative of the difference of the phases of f
1
and f
2
. The signal on line
112
charges charge pump
120
. When frequencies f
1
and f
2
are synchronized perfectly, the signal on line
112
may be at zero voltage and charge pump
120
may not be charged. Filter
130
is generally designed as a low pass filter to eliminate undesirable high frequency components. When the frequencies f
1
and f
2
are close, but not equal, line
123
will carry a voltage signal proportional to the difference in frequencies.
VCO
140
is designed to generate a clock signal with a predetermined frequency (equal to the desired clock frequency). The predetermined frequency equals f
2
×N, where N is the divisor in the frequency divider
150
. When f
2
is not an integral multiple of f
1
, a multiplier can be used to multiply frequency f
1
and the value of n is chosen to achieve the desired frequency f
2
. The frequency of VCO
140
is altered depending on the voltage level received on line
123
. The voltage level on line
123
is generated so as to achieve a synchronization of the frequencies f
1
and f
2
. The voltage level on line
123
may be amplified if needed to achieve such a synchronization.
Frequency divider
150
divides the frequency of clock signal received on line
145
by a factor of N. In a steady synchronized state, f
1
=f
2
and the clock frequency generated by VCO
140
equals N×f
1
. Thus, by a proper choice of N, a clock signal of a desired frequency can be generated.
PLL circuits such as the one described in
FIG. 1
are generally acceptable when the value of N is small (e.g., about 10). However, as the value of N becomes large, synchronizing the clock signal with the external time reference signal can become problematic as the correction of any misalignments between f
1
and the generated clock signal occurs only once every cycle of the reference clock f
1
.
The large correction times can be problematic in several environments such as display units which operate at high speeds. The absence of synchronization can result in display artifacts as is also well known in the art. For example, a television system may be used for displaying images encoded in television signals as well as images representative of services/data accessed on a network. One or more embodiments of such television systems are described in Related Patent 1 noted above.
In such systems, the display of network application data may need to be synchronized with the time reference signals associated with a television signal. To process and display network application data, clock signals having a frequency of as high as 40 MHZ may be required. The time reference signals of television signals can have a frequency of as low as 30 KHz. Thus, magnifications of the order of few hundreds to a thousand (N=100 to 1000) may be required. In such situations, PLL circuits such as the one described with reference to
FIG. 1
may not be acceptable.
Therefore, what is needed is a PLL circuit for generating a clock signal, which is synchronized well even in situations when the clock signal has a frequency substantially greater than the frequency of the external time reference signal. In addition, the PLL should operate in situations such as the television systems (e.g, those described in Related Patent 1) which provide combined display of television signal images and network application data image.
SUMMARY OF THE INVENTION
The present invention is directed to a clock generation circuit which generates a clock signal synchronized with an edge of an external time reference signal. The clock generation circuit is described in the context of a television system, which displays images encoded in television signals along with the images representing network application data. The clock signal is synchronized with the HSYNC signal of the television signal such that the points on the network application data images are accurately correlated with the points on the television signal images.
In one embodiment of the present invention, the clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. The PLL circuit includes a voltage controlled oscillator (VCO) driven by an error voltage generated by phase detector. The output of the VCO is a periodic signal having a frequency substantially equal to the frequency of the desired clock signal. The PLL circuit uses a high-quality high frequency oscillator to ensure that the periodic signal is closely synchronized with the internal reference signal. That is, close synchronization is maintained by designing the PLL circuit such that the periodic signal has a frequency which is a low multiple of the frequency of the internal reference signal.
The tracking block includes a resettable VCO (RVCO), which can be reset and restarted by asserting and deasserting a restart input. The RVCO is driven by the same error voltage of the PLL circuit, and is designed to generate the desired clock signal. A restart circuit asserts the restart input a short time before the expected arrival time of the edge of the external reference signal to stop the RVCO from generating the clock signal. The restart input is deasserted on the arrival of the edge of the external reference signal to restart the RVCO. Thus, the generated clock signal is synchronized with the external reference signal.
After being restarted, RVCO reaches a steady state in a short duration as the error voltage is computed in the PLL circuit. To prevent any glitches from being transmitted as the clock signal, a stop circuit is employed according to one aspect of the present invention. The stop circuit generates a stop signal a few clock cycles after the receipt of the edge of the time reference signal. The stop signal is provided as an input to an AND gate, which gates the output of RVCO as the clock signal only when the stop signal is not generated. The stop signal may be asserted a short duration prior to the arrival of the edge also. The stop signal operates to ensure that glitches are avoided in the generated clock signal. In addition, the stop signal can be asserted to ensure that only a desired number of clock cycles are generated during each period of the external reference signal.
Thus, the present invention provides a clock signal which is synchronized with an external reference signal. Synchronization may be achieved by stopping a RVCO from generating the clock signal, and restarting the clock signal generation synchronous with the reference signal.
The RVCO may not take substantial time to reach a steady state during the restarting process as the RVCO is driven by an error voltage generated in an external circuit (PLL).
Potential glitches in the clock signal are avoided by employing a gating circuit which does not provide the output of the RVCO as the clock signal a few cycles before receiving the edge of the time reference signal and a few cycles after restarting the RVCO.
Further features and advantages of the invention, as well as the structure and operation of various embodiments
Law Firm of Naren Thappeta
Lee Michael
TeleCruz Technology, Inc.
Yenke Brian P.
LandOfFree
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