Circuit and method for generating a buffered output having low d

Details Circuit and method for generating a buffered output having low d Circuit and method for generating a buffered output having low d

1993-11-09

1995-04-11

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327317, 327108, H03F 345

Patent

active

054061466

ABSTRACT:
A circuit and method provides a low distortion buffer by using a resistive divider stage (18, 20) and a gain stage (12) whose gain is equal to the inverse of the attenuation ratio of the resistive divider to provide unity gain. Multiple inputs (14, 42, 44, . . . 46) to the buffer circuit are accommodated by an input switching network (30, 38). The gain error introduced by the resistance of the switching network (30, 38) is canceled by placing an equivalent network (60) in a feedback path of the gain stage. The preferred circuit topology is well-suited to low-voltage applications and provides a low-distortion output. Circuits for reducing power consumption (68, 70) and minimizing undesirable transients (72) are also provided.

REFERENCES:
patent: 4720686 (1988-01-01), Westwick
Fiez, Terri S., Yang, Howard C., Yang, John J., Yu, Choung, and Allstot, David J., "A Family of High-Swing CMOS Operational Amplifiers", IEEE Journal of Solid-State Circuits, vol. 24, No. 6., Dec. 1989, pp. 1683-1687.

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