Circuit and method for gain error correction in ADC

Details Circuit and method for gain error correction in ADC Circuit and method for gain error correction in ADC

2007-09-17

2009-02-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000, C341S155000

Reexamination Certificate

active

07495589

ABSTRACT:
Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).

REFERENCES:
patent: 6037886 (2000-03-01), Staszewski et al.
patent: 6637886 (2003-10-01), Ushiyama et al.
patent: 6944219 (2005-09-01), Mathe
patent: 2004/0233086 (2004-11-01), Kiss et al.

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