Circuit and method for faster frequency switching in a phase...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

Reexamination Certificate

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Details

C331S017000, C331S17700V, C331S034000, C331S175000

Reexamination Certificate

active

07129791

ABSTRACT:
A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase/frequency detector that detects phase/frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and/or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and/or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.

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patent: 5334952 (1994-08-01), Maddy et al.
patent: 5357215 (1994-10-01), Greiderer
patent: 5389899 (1995-02-01), Yahagi et al.
patent: 5420545 (1995-05-01), Davis et al.
patent: 5656975 (1997-08-01), Imura
patent: 6621356 (2003-09-01), Gotz et al.
patent: 6717475 (2004-04-01), McCarthy
patent: 2002/0153959 (2002-10-01), Gotz et al.
patent: 42 16 714 (1993-12-01), None
patent: 0 582 390 (1994-02-01), None
patent: 0 993 122 (2000-04-01), None
patent: WO 95/13666 (1995-05-01), None

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