Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-08-21
2001-07-10
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06260056
ABSTRACT:
BACKGROUND OF THE INVENTION
It is often necessary to compute the square of an n-bit value. Conventional squaring circuits use a single multiplier that receives and squares the n-bit value. Unfortunately, the larger the bit length n of the value, the slower and larger the single multiplier. It is desirable to increase the squaring speed and reduce the size of the squaring circuit.
SUMMARY OF THE INVENTION
In accordance with the invention, a squaring circuit includes an input terminal that is configured to carry a k-bit input bit group representing a k-bit input value. The k-bit input bit group has a left hand m-bit portion and a right hand n-bit portion representing respective left and right hand values. A left hand squaring circuit is configured to receive the left hand m-bit portion and generate a first term bit group representing a square of the left hand value. A multiplier is configured to multiply the left hand m-bit portion and the right hand n-bit portion to generate a second term bit group representing a product of the left and right hand values. A right hand squaring circuit is configured to receive the right hand n-bit portion and generate a third term bit group representing a square of the right hand value. An adder is configured to add the second term bit group (left shifted by n+1 bit positions) to a concatenation of the first and third term bit groups. The adder generates a square of the k-bit input value based on the addition. In accordance with the invention, a method includes providing the above-described circuit.
In accordance with the invention, a method includes splitting an input bit group representing an input value into left and right hand portions representing respective left and right hand values. A first term bit group is generated representing a square of the left hand value. A second term bit group is generated representing a product of the left and right hand values. A third term bit group is generated representing a square of the right hand value. The first and third term bit groups are concatenating to provide a concatenated bit group. The concatenated bit group and the second term bit group are added to generate an output bit group representing a square of the input value.
The principles of the present invention will more fully be understood in light of the following detailed description and the accompanying claims.
REFERENCES:
patent: 4313174 (1982-01-01), White
patent: 4787056 (1988-11-01), Dieterich
patent: 5629885 (1997-05-01), Pirson et al.
patent: 5957999 (1999-09-01), Davis
patent: 6032169 (2000-02-01), Malzahn et al.
ATI International SRL
Kwok Edward C.
Mai Tan V.
Skjerven Morrill & MacPherson LLP
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