Circuit and method for extracting signalling information embedde

Details Circuit and method for extracting signalling information embedde Circuit and method for extracting signalling information embedde

1986-06-11

1987-10-20

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 312

Patent

active

047019131

ABSTRACT:
The circuit comprises a serial to parallel converter for extracting the signalling bits from the various channels of the data streams and for providing a serial stream of signalling bits, and a read-write memory having a plurality of locations at least as large as the number of channels in the data streams, each location having at least the number of cells necessary to store a byte of signalling data and the signalling message header. The converter outputs the signalling bits from consecutive channels of the data streams into a one-byte shift register adapted to shift the bits laterally as well as receive and output a byte of data in parallel from and unto a bus connected to memory. A control circuit is responsive to clock signals for providing timing control signals whereby for each signalling bit outputted from the serial to parallel converter, the memory location associated with the channel of that bit is read into the shift register, the signalling bit is shifted laterally into the register and its contents is written back into the memory. On the last bit of each byte of the signalling message, that byte is fed to an output buffer and then to a message handler circuit. There is included, circuitry for recognizing a signalling message header, full bytes of signalling data and the end of a signalling message.

REFERENCES:
patent: 4002846 (1977-01-01), Barbier
patent: 4135060 (1979-01-01), Heckel et al.
patent: 4627047 (1986-12-01), Pitroda et al.

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