Circuit and method for erasing flash memory array

Details Circuit and method for erasing flash memory array Circuit and method for erasing flash memory array

1997-12-11

1999-07-27

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

3651853, 36518533, 365218, G11C 1604, G11C 700

Patent

active

059301740

ABSTRACT:
A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

REFERENCES:
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5600593 (1997-02-01), Fong
patent: 5642311 (1997-06-01), Cleveland et al.
Endoh, T. et al., "New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics," IEDM, Apr. 1992, pp. 603-606.
Oyama, K. et al., "A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond," IEDM, Apr. 1992, pp. 607-610.
Miyawaki, Y. et al., "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16Mb/64Mb Flash EEPROMs," Symposium on VLSI Circuits, 1991, pp. 85-86.

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