Circuit and method for erasing EEPROM memory arrays to prevent o

Details Circuit and method for erasing EEPROM memory arrays to prevent o Circuit and method for erasing EEPROM memory arrays to prevent o

1990-04-16

1992-06-16

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1140

Patent

active

051229854

ABSTRACT:
The device and process of this invention provide for elininating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

REFERENCES:
patent: 4958321 (1990-09-01), Chang

Affiliated with

Also associated with

Rating

Circuit and method for erasing EEPROM memory arrays to prevent o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for erasing EEPROM memory arrays to prevent o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for erasing EEPROM memory arrays to prevent o will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1758888