Circuit and method for erasing EEPROM memory arrays to prevent o

Details Circuit and method for erasing EEPROM memory arrays to prevent o Circuit and method for erasing EEPROM memory arrays to prevent o

1994-06-15

1999-05-11

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 3651853, G11C16/04

Patent

active

RE0362107

ABSTRACT:
The device and process of this invention provide for eliminating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

REFERENCES:
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3744036 (1973-07-01), Frohman-Bentchkowsky
patent: 3938108 (1976-02-01), Salsbury et al.
patent: 4181980 (1980-01-01), McCoy
patent: 4209849 (1980-06-01), Schrenk
patent: 4247918 (1981-01-01), Iwahashi et al.
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4334292 (1982-06-01), Kotecha
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4377857 (1983-03-01), Tickle
patent: 4397000 (1983-08-01), Nagami
patent: 4400799 (1983-08-01), Gudger
patent: 4404577 (1983-09-01), Cranford, Jr. et al.
patent: 4434478 (1984-02-01), Cook et al.
patent: 4435790 (1984-03-01), Tickle et al.
patent: 4460982 (1984-07-01), Gee et al.
patent: 4689787 (1987-08-01), Hotta
patent: 4766473 (1988-08-01), Kuo
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 4792925 (1988-12-01), Corda et al.
patent: 4807003 (1989-02-01), Mohammadi et al.
patent: 4858194 (1989-08-01), Terada et al.
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 4875188 (1989-10-01), Jungroth
patent: 4888734 (1989-12-01), Lee et al.
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4958317 (1990-09-01), Terada et al.
patent: 4958321 (1990-09-01), Chang
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4996571 (1991-02-01), Kume et al.
patent: 5022001 (1991-06-01), Kowalski et al.
patent: 5043940 (1991-08-01), Harai
patent: 5047981 (1991-09-01), Gill et al.
patent: 5060195 (1991-10-01), Gill et al.
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5177705 (1993-01-01), McElroy et al.
patent: 5293560 (1994-03-01), Harari

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