Circuit and method for equalization of signals received over...

Wave transmission lines and networks – Automatically controlled systems – With control of equalizer and/or delay network

Reexamination Certificate

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C333S02800T, C375S230000, C330S304000

Reexamination Certificate

active

06531931

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to receivers connected to transmission lines and more specifically to a receiver circuit for compensating for signal loss caused by a transmission line.
2. Prior Art
Coaxial cables exhibit a skin effect which attenuates transmitted signals based on their frequency. The amount of attenuation in decibels (db) increases in proportion to the square root of the frequency f of the transmitted signal. Additionally, the coaxial cable length and diameter, the ambient temperature, and other factors affect attenuation of signals.
Equalization amplifiers are used to compensate for signal attenuation. Ideally, the equalization amplifier transfer function is the inverse of the transfer function representing the degree of signal attenuation in the transmission line. This enables recovery of data signal components (e.g., high frequency components) which have been attenuated by the transmission line.
Conventional equalization circuits are described in U.S. Pat. No. 5,115,213 to T. Eguchi; U.S. Pat. No. 4,187,479 to K. Ishizuka; U.S. Pat. No. 4,689,805 to S. Pyhalammi et al.; U.S. Pat. No. 5,036,525 to H. Wong; U.S. Pat. No. 4,275,358 to W. A. Winget; U.S. Pat. No. 4,378,535 to R. F. Chiu et al.; U.S. Pat. No. 4,768,205 to K. Nakayama; U.S. Pat. No. 5,337,025 to G. D. Polhemus; U.S. Pat. No. 5,293,405 to J. E. Gersbach et al.; U.S. Pat. No. 4,459,698 to O. Yumoto et al.; U.S. Pat. No. 4,583,235 to J. Domer et al.; U.S. Pat. No. 4,243,956 to M. Lemoussu et al.; U.S. Pat. No. 4,961,057 to S. Ibukuro; and in Giacoletto, L. J. (editor), Electronics Designersí Handbook (2nd ed.), McGraw-Hill Book Company, New York, N.Y. (1977).
A conventional equalization linear channel provides a single filter having a fixed transfer function which provides optimal equalization for a limited range of cable lengths. A filter whose transfer function is optimized for shorter cables will not be as optimal for longer cables. Similarly, a filter whose transfer function is optimized for long cables will not be as optimal for shorter cables.
Typically, an equalization linear channel, for short cables can be coupled in series with another short cable equalization linear channel to provide equalization for a longer cable. However, equalization imperfections occurring in the first stage are magnified by the second stage, resulting in non-optimal performance for a long cable. Also, each equalization stage consists of several amplifiers so coupling equalization stages in series puts numerous amplifier stages in series. Each amplifier stage loses some of the signal bandwidth, particularly at high frequencies, which reduces the bandwidth of the entire linear channel, thereby reducing the signal-to-noise ratio and the optimization for long cable equalization.
The problem of amplifier bandwidth loss is aggravated in amplifiers built using commercially available Complementary-Metal Oxide Semiconductor (CMOS) processes due to the lower tranconductances and higher offsets of Metal Oxide Semiconductor (MOS) devices compared to bipolar devices. The gain bandwidth product of CMOS amplifier structures is typically lower than that of bipolar amplifier structures.
A transmission cable typically has a frequency independent (or DC) loss which is a linear function of the cable length. An equalization architecture should restore the DC component lost in the cable and output a signal having an amplitude close to that of the originally transmitted signal. An adaptive equalization algorithm which is peak-dependent demands that the equalized output signal peak be very close to that of the originally transmitted signal before cable attenuation. Algorithms which are peak-independent are preferable but it remains important to restore as much as possible of the lost DC component to maximize the signal-to-noise ratio.
Conventional adaptive equalization systems also suffer from a problem known as “baseline wander” which occurs when using differential signal transmission (i.e., MLT-3 coding) over a twisted pair medium. MLT-3 coding systems use three voltage levels (i.e., +1V, 0V, and −1V) relative to a return voltage, referred to as the baseline or baseline reference which is typically set to ground. In practice, the baseline does not remain at ground, but instead wanders up and down, which is referred to as “baseline wander.”
What is needed is an equalization linear channel architecture which can be implemented in a commercially available CMOS process, which can provide optimum filter transfer characteristics over a wide range of cable lengths and which has sufficient bandwidth over a wide frequency range even when operating with a low (3 volt) supply voltage. This architecture should also restore most of the originally transmitted signal amplitude in order to maximize the signal-to-noise ratio.
SUMMARY OF THE INVENTION
The present invention provides equalization of signals received over a communication system transmission line. The invention includes an equalization linear channel having an input biasing stage, a linearity amplifier stage, a first DC gain stage, a second DC gain stage, a DC multiplier stage, an AC/DC gain stage, and a gain buffer stage.
The present invention is advantageous in that it provides an equalization linear channel which, over an exceptionally wide range of cable lengths, can optimally equalize waveforms to provide equalized waveforms close in amplitude to the transmitted waveforms independent of DC cable loss, thus maintaining a good signal-to-noise ratio. The circuit architecture comprises only a few amplifier stages in series and can be fabricated using well-known CMOS processes. The stages are transconductance amplifiers which are simple in construction, leading to a high bandwidth in each stage and improved immunity to both offset and power supply noise effects. The circuit architecture performs consistently over wide variations in temperature, power supply, and process, and can be implemented readily with either 3 volt or 5 volt power supplies. The 3 volt power supply architecture provides recognized power and system advantages over a 5 volt power supply.


REFERENCES:
patent: 5115213 (1992-05-01), Eguchi
patent: 5337025 (1994-08-01), Polhemus

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