Reexamination Certificate
1998-05-14
2001-05-08
Wells, Kenneth B. (Department: 2816)
C365S225700
Reexamination Certificate
active
06227637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductors and more particularly to a method and circuit for encoding a bit of information in a semiconductor device utilizing a fuse circuit with an alterable impedance.
2. Description of the Relevant Art
Semiconductor devices have been widely utilized in the electronics industry for an enormous variety of functions and tasks since the introduction of commercially feasible integrated circuits in the early 70's. A semiconductor device is typically characterized by a large number of individual circuit elements such as transistors, diodes, capacitors, and resistors all fabricated essentially simultaneously on a common monolithic semiconductor substrate such as single crystal silicon. Once fabricated, these individual circuit elements are then selectively connected to one another with one or more levels of patterned interconnect layers to achieve a desired functionality. Among the many varieties of devices fabricated using semiconductor technology are the microprocessors, controllers, and memory devices well known to designers, manufacturers, and users of personal computers and workstation as well as an enormous number of other types of devices.
The essential characteristics of fabrication processes employed to manufacture semiconductor devices are as well known within the semiconductor industry as the devices themselves. It is sometimes useful to describe a semiconductor fabrication process as having a “front end” in which the active areas of the device are defined and the individual circuit elements are produced and a “back end” in which the individual circuit elements are selectively coupled to one another through the use of interconnect levels. Both the front end and back end typically include process sequences in which a desired pattern is deposited upon, etched into, or grown within the underlying structure through the use of well known deposition, photolithography, and etch processes. Each photolithography sequence includes the selective exposure of a photoresist material. This selective exposure is overwhelmingly accomplished by accurately positioning a photomask comprised of opaque and transparent regions that define the desired pattern between an unexposed photoresist layer deposited on the device substrate and an exposing radiation source such as a mercury vapor lamp. One measure of the complexity and cost of any given semiconductor fabrication process is the number of these so called “mask” steps required to produce a given device. All else being equal, fewer mask steps are always preferable to more mask steps because of the enormous cost of the photoalignment equipment and the time required to complete each mask step. Despite this preference for fewer mask steps, it is not uncommon to encounter multiple interconnect level CMOS processes that require in excess of twenty mask steps. Manufacturers therefore typically resist introducing new elements that require additional mask steps into a fabrication process.
Semiconductor fabrication processes are most commonly accomplished using large circular wafers as the starting material. Because these wafers comprise an area that is typically much larger than the area required to produce the desired device, an array of devices is typically fabricated on each wafer. Each of the individual devices is commonly referred to as a “die.” Most mask steps in modern fabrication processes are of the “step and repeat” variety in which only one die is exposed at any time. The photoalignment equipment exposes the entire array of die by stepping the photomask through the entire array. It will be appreciated that, as a result of this exposure technique, each die would be essentially identical to each other die on the wafer but for randomly occurring defects that are generated during every manufacturing process. While this uniformity is generally highly desirable, semiconductor manufacturers would occasionally prefer to encode unique information into each die. If, for example, a semiconductor manufacturer wanted to encode a unique and electrically detectable serial number or other useful information into each device, a mechanism for incorporating this unique information into each die would be required. In some cases, the incorporation of such a mechanism might be compatible with the particular fabrication process used to fabricate the associated integrated circuit. Incorporating a unique information mechanism into a process used to fabricate an electrically programmable read only memory (EPROM), as an example, would be relatively easy to accomplish without increasing the complexity of the process because the EPROM process already requires the process steps necessary to implement such a mechanism. More particularly, because the EPROM process requires a floating gate and other circuit elements necessary to produce and program an EPROM cell, the unique information mechanism itself could be comprised essentially of a dedicated section of EPROM cells. The process technologies used to fabricate the great majority of devices, however, do not readily avail themselves of a technique by which a unique information storage mechanism could be incorporated into the device. In addition, even in the case of EPROMs, it would be highly desirable if the implemented mechanism consumed the smallest amount of area possible. EPROM circuits and other circuits that would require the generation of large drive currents to effect an essentially permanent change in the circuit generally require a relatively large area require area to implement.
Accordingly, it would be highly desirable to incorporate a mechanism by which unique information could encoded into each device without significantly increasing the complexity or cost of the fabrication process used to manufacture the device and without introducing complex circuitry that consumes relatively large areas of the die.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a method and circuit for encoding and electrically detecting a bit of information in a semiconductor device. The invention contemplates the incorporation of a fuse circuit that can be fabricated without increasing the complexity of the fabrication process and yet consumes a relatively small area of the device. The impedance of the fuse circuit is alterable and the invention is configured to produce an output signal that is indicative of the fuse circuit impedance thereby conveying a bit of information.
Accordingly, it is an object of the present invention to provide a circuit suitable for encoding and retrieving a bit of information from an integrated circuit. It is a further object to provide for an information circuit that is manufacturable with existing semiconductor fabrication processes. It is a further object to provide an information circuit in an integrated circuit that consumes a relatively small area of the device. It is a further object of the invention to provide for a method for encoding and retrieving a bit of information within a semiconductor integrated circuit.
Broadly speaking, the present invention contemplates an information circuit in a semiconductor device. The information circuit is suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor. These elements of the output circuit are coupled in series between a power supply terminal and a ground terminal. An output node of the information circuit is coupled to the output circuit. The information circuit is configured such that the output node voltage is indicative of the impedance of the fuse circuit when the input node is biased to a “read” state, the power supply terminal is biased to a power supply voltage, and the ground terminal is grounded. Accordingly, by setting the
LSI Logic Corporation
Wells Kenneth B.
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