Circuit and method for eliminating idle cycles in a memory devic

Details Circuit and method for eliminating idle cycles in a memory devic Circuit and method for eliminating idle cycles in a memory devic

1999-04-12

2000-05-16

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523008, 36523002, 36518901, G11C 800

Patent

active

060646241

ABSTRACT:
A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

REFERENCES:
patent: 5377338 (1994-12-01), Olson et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5572467 (1996-11-01), Ghassemi et al.
patent: 5717904 (1998-02-01), Ehlers et al.
patent: 5757704 (1998-05-01), Hachiya
patent: 5793688 (1998-08-01), Mclaury
patent: 5917772 (1999-06-01), Pawlowski

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