Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-03-14
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S230020, C365S189011
Reexamination Certificate
active
06215724
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to an input circuit to be used, for example, in a memory device, and a method for operating the input circuit and memory device. More particularly, the present invention is directed to an input circuit and method that eliminates idle cycles in a memory device through the use of input registers.
2. Description of the Background
Memory devices, such as static random access memories (SRAMs), typically include a memory array for storing data, an address circuit for accessing the memory array, a write circuit for writing data to the memory array, and a read circuit for reading data from the memory array. In pipelined memory devices, data is typically read from a memory array during one clock cycle and provided on the data bus during the next clock cycle. Similarly, data to be written to a memory array is typically latched from the data bus during one clock cycle and written to the memory array during the next clock cycle. As a result, in a pipelined memory device a read operation followed by a write operation will typically require that the memory device be idle for at least one clock cycle while a previous operation is completed and the next operation is begun. Those idle cycles can significantly reduce the operating speed of a memory device.
Thus, the need exists for a pipelined memory device in which idle cycles during data transfers to and from the memory device are eliminated.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a data input circuit. The input circuit includes a first data input register, a second data input register, and a write driver connected to the first and second data input registers. The first and second data input registers are preferably series-connected and, in the preferred embodiment, a multiplexer selectively connects one of the first and second data input registers to the write driver.
The present invention may be embodied as a memory device, including an address circuit, a write circuit, a memory array, and a read circuit. The write circuit includes first and second data input registers and is constructed in accordance with the present invention. The memory array is connected to the address circuit, the write circuit, and the read circuit. Memory devices constructed in accordance with the present invention may also be used to form a memory system.
The present invention is also directed to a method of operating a memory device. The method includes storing data associated with a first address, storing data associated with a second address, storing data indicative of the first address, storing data indicative of the second address, executing a read operation, and executing a write operation. Executing a write operation is performed without resulting in an idle cycle between the read operation and the write operation. Executing a write operation also uses data associated with one of the first and second addresses, and uses data indicative of one of the first and second addresses. The order of executing the method may be interchanged, as will be understood from the detailed description provided hereinbelow.
The present invention solves problems experienced with the prior art because it eliminates idle cycles between read and write operations in a memory device, thereby increasing the bandwidth of the device. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.
REFERENCES:
patent: 5377338 (1994-12-01), Olson et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5572467 (1996-11-01), Ghassemi et al.
patent: 5717904 (1998-02-01), Ehlers et al.
patent: 5757704 (1998-05-01), Hachiya
patent: 5793688 (1998-08-01), Mclaury
patent: 5917772 (1999-06-01), Pawlowski
patent: 6064624 (2000-05-01), Pawlowski
Kirkpatrick & Lockhart LLP
Lam David
Micro)n Technology, Inc.
Nelms David
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